clk_pll input location for DDR4 HPS (arria10sx066f34I2SG)

[BJona]

Hi I'm working on the device mentionned in the title.

I'm using a board from a third party vendor, but I'm facing a problem concerning the input clock of the HPS ddr interface.

When trying the plan stage, Quartus(19.3pro) don't let me place this pin at the location AL27 resulting in an error. I don't understand why Quartus doesn't want to fit this pin at this particular location as there is no explanation in the error tab.

The problem is that I can't place this particular pin at the proposed location because it's already binded to another clock of the board.

Thank you for your help

[sstrell]

For HPS DDR, you have to use specific pins for a specific I/O bank since the interface is all hardened and dedicated to the HPS. If there's already a clock not used by the memory interface going into that particular pin, you'll have the issue you're seeing.

#iwork4intel

[BJona]

Hi sstrell,

I understand, I think this is a conception bug.

[EBERLAZARE_I_Intel · Accepted solution]

Hi there,

I apologize for the late reply, due to Lunar New Year.

Please try the following:

1. You will need below INIs variable :

• emif_restrict_hps_refclk_to_ac_tile=off

1. Open the fitter_error.qar file, add the INI file with emif_restrict_hps_refclk_to_ac_tile = off.

2. Then re-check the fitter.

Could you please try using these INIs and let us now if the error disappears when placing an HPS-EMIF?

2. If not, could you try using Quartus 19.1 if are you seeing the same error? Please let us know if the error the same when using Quartus 19.1.

Regards.

[BJona]

Hi el.ign,

thank you for you reply, this solved my problem.

Best regards,

John