clock gate cell and constrains

[lGuo01]

​I'm using ARRIA10 FPGA, RTL Latch based  gate clock have to be used because there is no enough gate clock cells ALTCLKCTRL

 in this FPGA. the RTL gate cell is shown below.

             always @(*)

                 if(~clk_in) q = clk_en;

              assign clk_out = clk_in& q;

 If the gate clock is identified by Quartus, does it need  constrain to check it? if yes, what the clock constrain looks like?

Thanks

Vincent

[Rahul_S_Intel1]

Hi, You can mentioned it in the SDC file, normally the IO pin that is chose is recommended to dedicated clock pin