clock jitter simulation of LVDS IP

[arife]

Hi,

I am using LVDS RX IP with 1.6 Gbps data rate with 800MHz inclock frequency. I would like to check jitter performance in simulation. I have created a a testbench that applies jitter 5ps constant. If I apply more than 5ps, pll_locked signal can not get locked. But 5ps is too small according to documentations it should be more. I am adding the simulation waveforms. Ideal clock period should be 1250 ps, but I am applying first 1242 ps then 1258 ps and keep repeating in the same order.  Am I applying the jitter correctly or IP can not handle it in simulation?

[skbeh]

To have a reliable recovery lock after disturbed input clock, users can enable self-reset by setting the "Enable self-reset on lost lock in PLL" option.

LVDS SERDES Transmitter/Receiver IP Cores User Guide mentions of this option,

(https://www.intel.com/content/www/us/en/docs/programmable/683062/17-1/lvds-serdes-transmitter-receiver-ip-36681.html)

'Enable self-reset on lost lock in PLL': 

Turn on this option to reset the PLL automatically whenever the PLL loses lock.

This option is available only for Arria II GX, Arria II GZ, HardCopy III, HardCopy IV, Stratix III, and Stratix IV

devices when SERDES is implemented in logic cells, and for Cyclone lll, Cyclone IV, and Intel Cyclone 10 LP devices.

[arife]

Hello,

Actually I am using Arria 10 GX and also my problem is not PLL losing lock, it never get locked from the beginning.  How much jitter I can apply in simulation?

[skbeh]

As I understand, when using LVDS RX SERDES IP with RX non-DPA mode, inclock source must be source from dedicated clock pin, cannot source from non-dedicated IO PLL output clock.

Suspect that the PLL is not able to detect the clock correctly which cause the PLL not able to locked at 800Mhz.

The suggestion is to try first with lower inclock (i.e. 200Mhz) to see if the PLL can lock.