I have a few clock signals as input and would like to internally multiplex them and generate one clock output that clocks an external device. Is it safe to use logic (LUT) muxers for a clock, knowing that I don't change the muxer selection when the clocks are enabled? Unfortunately the dedicated clock control block in the MAX10 has a limited number of inputs.
It is recommended to use dedicated hardware to perform clock multiplexing when it is available, instead of using multiplexing logic. For example, you can use the clock-switchover feature or clock control block available. These dedicated hardware blocks ensure that you use global low-skew routing lines and avoid any possible hold time problems on the device due to logic delay on the clock line.
Thanks YY. I understand that it is recommended to use dedicated blocks. Unfortunately I need to multiplex a clock signal coming from a non dedicated external pin so I cannot use the dedicated block. My question is if it is safe to use a logic multiplexer to do so. Please note that I do not intend to switch the multiplexer input when the clock is enabled.
Any signal, even if it's not coming from a dedicated clock pin, can connect to the clock resources mentioned. There will be some added delay that you can see in the timing analyzer, but the resources can still be used.
not really! I tried that on the clock muxer in the clock control block but it did not route.
You will get error ID:15660
According to the user guide, clock multiplexing can introduce glitches that create functional problems, and the delay inherent in the combinational logic can lead to timing problems. If you implement a clock multiplexer in logic cells because the design has too many clocks to use the clock control block, or if dynamic reconfiguration is too complex for your design, it is important to consider simultaneous toggling inputs and ensure glitch-free transitions. Kindly refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51007.pdf
Figure 13–3. Glitch-Free Clock Multiplexer Structure in
Example 13–48. Verilog HDL Clock Multiplexing Design to Avoid Glitches