clock problem on De0 nano board (schematics file)

[Altera_Forum]

hello,  

 i don't have seen the same problem with a good solution, so i ask here,  I try to do a counter which is suposed to count to ten at 1Hz but i have a warning i can't solve alone,   I have this warning :   Warning (21074): Design contains 1 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "CLOCK_50"  https://alteraforum.com/forum/attachment.php?attachmentid=13918&stc=1   thank you very much !

[Altera_Forum]

It's just a warning, not an error. It can be safely ignored.

[Altera_Forum]

You have missed something if no output dependent on input pin "CLOCK_50"... 

Are you doing an asynchronous design?

[Altera_Forum]

Why is there vcc text near the clock_50 flag near the left side of your schematic Under the input text)? 

 Is your clock net accidentally connected to vcc? If so the message makes sense, as no logic is then dependent on the input clock_50, and that one input does not drive any logic.  I would check the schematic, and if possible the generated text nextlist, of your design. I suspect that clock_50 is not really connected.

[Altera_Forum]

Ah, I missed the VCC. That's probably the issue.