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Valued Contributor III
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continuous assignment on port list fails

Hello, 

 

Had a module with an output tied high, e.g:module a( 

output wire b = 1'b1); 

... 

 

Quartus 16.1 synthesizes to 1'b0. Is this to be expected by the LRM? I couldn't find anything explicit on the publicly available SV LRMs. 

 

Of course, when I re-code it works as expected:module a( 

output wire b); 

assign b = 1'b1; 

... 

 

Thanks, sysTom
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Valued Contributor III
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I'm not sure that is valid syntax in a port declaration (continuous assignment to a wire). 

 

This should work: 

module a( 

output reg b = 1'b1); 

 

I think the issue is not that: output wire b = 1'b1 should work, but rather it should throw an error.
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Valued Contributor III
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You're right in that map does report 

 

Warning (10034): Output port "b" at a.v(#) has no driver 

 

When I change to reg type as you suggest it gets the same as I would suspect since a declaration assignment to a 'reg' type is not continuous - it's just an initial value. 

 

It certainly works on ncsim - I can try lint, DC shell and modelsim to see if anybody else complains. 

 

Thanks, sysTom
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