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Dear All,
could someone advice, how to convert single bit information into integer so I could use it as index to an array? Conversion of std_logic_vector/unsigned/signed vectors is easy is there any way how to do following using only numeric_std library? ASamplexDY(to_integer(IsISamplexS)) <= DxDY; where IsISamplexS is type std_logic Of course the line above does not work as there is no function to_integer which would take std_logic. If I try to convert first to unsigned, it does not work either because it is not vector. One can do trick like this: AVERAGERS : process (ClkxC, ResetxRNA) is variable vMessxD : std_logic_vector(1 downto 0); --! bleh begin -- process AVERAGERS if ResetxRNA = '0' then --! asynchronous reset (active low) ASamplexDY <= (others => (others => '0')); elsif rising_edge(ClkxC) then --! rising clock edge vMessxD := '0' & IsISamplexS; -- we are inside the processing of the I sample: if SwitchSignxS = '0' then ASamplexDY(to_integer(unsigned(vMessxD))) <= DxDY; else ASamplexDY(to_integer(unsigned(vMessxD))) <= ASamplexDY(to_integer(unsigned(vMessxD))) + OpositeSignDataxM; end if; end if; end process AVERAGERS; but it looks ugly and stupid. thanks .d.Link Copied
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there are a couple of methods.
Convert it to unsigned by implicitly making it an array: ASamplexDY(to_integer( unsigned'("" & IsISamplexS) )) <= DxDY; here, the ( "" & IsISamplexS ) makes it an array of length 1, and the unsigned' qualifies it as an unsigned because it could be signed or unsigned. Secondly, write a conversion function yourself:
function to_integer( s : std_logic ) return natural is
begin
if s = '1' then
return 1;
else
return 0;
end if;
end function;
ASamplexDY(to_integer( IsISamplexS )) <= DxDY;
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cool. thanks.
exactly what I needed. true I did not think of writing a function ...- Mark as New
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I just thought Id show off a little bit, just to show you the things you can do with VHDL. There is nothing forcing you to using integers for arrays. You can actually use any enumerated type. eg:
type sl_array_t is array( std_logic range <> ) of integer;
signal my_array : sl_array('0' to '1');
signal sel : std_logic;
output <= my_array(sel);
This way, if sel ever becomes anything other than '0' or '1' during simulation, you will get an array index out of bounds exception. Quartus should synthesise this, Ive tested arrays using the character type as the arary index before, and it infered me a ram.
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A quite workable solution is to use a
std_logic_vector(0 downto 0) as intermediate. This saves you the annoying "if (bit_x='1') then ...; else ...; endif;" Example: variable i: integer; variable a_bit : std_logic; variable a_bitx : std_logic_vector(0 downto 0); variable s: line; .. -- integer to bit: i := 1; a_bitx <= std_logic_vector(to_unsigned(i,1); a_bit <= a_bitx(0); -- long alternative: if i=1 then a_bit <= '1'; else a_bit <='0'; endif; -- and bit to e.g. text: write(s, to_integer(unsigned(a_bitx))); -- long alternative: if a_bit = '1' then write(s, string'("1")); else write(s, string'("0")); endif; NOTE: Often, in a testbench, the std_logic a_bit is not needed anymore if you use a_bitx(0) instead
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