I am dealing with Verilog HDL. Could you please explain how to convert a logic element as an arithmetic mode.In cyc2 handbook it says that, "The arithmetic mode is ideal for implementing adders, counters, accumulators, and comparators. An LE in arithmetic mode implements a 2-bit full adder and basic carry chain" But my codes use more than one logic element.
If you study the Cyclone II (or Cyclone III - IV) LE schematic thoroughly, you'll realize, that it can't implement 2-bit full adder, which is according to general comprehension a logic circuit comprised of to full adders. As a sufficient reason, the LE has only one output bit. So obviously, the handbook author means a full adder with two input bits, which is usually designated a 1-bit full adder.Strange enough, the erroneous statement has been continued form Cyclone II up to Cyclone IV handbook. So you actually need one LE for each output bit. In addition, you need LEs to connect both Cin and cout, that can be only routed to other carry signals directly. As a result, e.g. a 16-Bit adder needs 18 LEs. For a two bit adder,you can't achieve less than 4 LEs, as your fadder2 and fadder3 do. To avoid misunderstandings about the indended logic, I suggest a MegaWizard generated adder or a behavioral design.