cyclone 10 LP true LVDS transmitter IO banks

[MrLamb]

HI there,

I am considering to use Cyclone 10 LP for LVDS communication. I am confused the information of official document for explaining the true LVDS transmitter at IO banks.

Although figure 73 description says the location indicates "Top and Bottom", both sides, the description about Figure 72, there is no mention about on the 'LEFT' side but only on "RIGHT" side banks.  Does it mean that LEFT banks does not have true LVDS output buffer?

On below page, 

https://www.intel.com/content/www/us/en/docs/programmable/683777/current/lvds-i-o-standard-in-devices.html

"The Intel® Cyclone® 10 LP left and right I/O banks (row I/Os) support true LVDS transmitters. The top and bottom I/O banks support emulated LVDS transmitters with external resistors.

For the LVDS receiver, you require an external 100 Ω termination resistor between the two signals at the input buffer.

Figure 72. LVDS Interface with True Output Buffer on the Right Side I/O Banks

Figure 73. LVDS Interface with External Resistor Network on the Top and Bottom I/O Banks

"

Thank you.

JL

[Farabi]

Hello,

True LVDS is a buffer built originally for LVDS(which by default comes together in pair, Rx and Tx buffer), while the other LVDS is an normal IO with paired buffer to form an LVDS like function.

regards,

Farabi

[AqidAyman_Intel]

Hello JL,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,

Aqid Ayman