- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
请问cyclone 5有没有通过fPLL(altera PLL ip)生成transceiver时钟,好像这个模式会出现很多Quartus fitter error, 有没有用的IP是 Transceiver Native PHY Intel Cyclone V
Link Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
You may generate the transceiver clock through fpll. For further information, you may refer to link below, https://www.intel.com/content/www/us/en/docs/programmable/683586/current/internal-clocking.html
Best regards,
Zi Ying
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Since no hear any feedback from you, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.
Best regards,
zying

Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page