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cyclone IV GX PCIE

JPENG4
Beginner
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add&data.pngSequence diagram.jpgreg.pngThe principle diagram.jpg

 

 1、QSYS is used to call the PCIE core to communicate with PC, and the PCIE core communicates through the avalon-mm bus and the local interface (self-programmed), which can realize subsequent data reading and writing, and the corresponding address of all data is offset by two digits.

2、I wonder if there is a place to set in the driver.Or maybe I'm using the wrong Avalon bus。

3、here is another possibility. Is there a 2-bit offset in the address of PCIE?

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SengKok_L_Intel
Moderator
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Hi, In order to better assist you, it will be great help if you can descript your questions in detail. If you would like to understand more about the Avalon specification, I would suggest you to refer to this link: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf Regards -SK Lim
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