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Honored Contributor I

cyclone iii interface to pcie without additional PHY IC or only 4:1 serdes IC?

Hi, does anybody know if it's possible to have a Cyclone III act as a PCI Express master without additional interface ICs? 


The PCIe physical layer is just LVDS with clock recovery, both of which are features supported by CycloneIII. The only issue I see is that the slowest PCIe channels run at 2.5gbit/sec whereas CycloneIII tops out at 875mbit/sec. So, I'm wondering, 


1. Is it possible to interface the CycloneIII directly to a PCIe slave and simply run the bus clock (which the master determines, if I recall) slower than normal? 


2. If (1) won't work, would adding a 4:1 LVDS SERDES work? This takes the incoming 2.5gbit/sec LVDS pair and produces outgoing four 0.875gbit/sec pairs. Another SERDES would be needed for the transmit direction. For the RX direction the SERDES can be avoided by using four LVDS pairs on the cyclone with their clocks phase-shifted by multiples of 90 degrees, but that trick won't work for TX so the SERDES IC would be necessary there. 


Our application requires only a tiny fraction of the PCIe bandwidth, so running the link at ridiculously low speeds is not a problem. Unfortunately the other side of the link has to be PCIe (slave). 


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