ddr bi-directional with different input/output clocks

[Altera_Forum]

Greetings, I am wondering what the correct megafunctions/primitives are for implementing input/output dual-data-rate data lines for a DDR memory device. I'm on a Cyclone IV. 

 Here are my requirements:  1) Need to be able to tri-state the line to implement bi-directional 2) Need to output with dual-data rate, clocked from my internal clock 3) Need to input dual-data rate, clocked from the DDR's DQS (data strobe).  It seemed like the ALTDDIO_BIDIR was going to work, as it has an inclock, outclock, oe, and inclocken (can ignore DQS when in non-read states), but the simulation shows that I was only capturing input data on the rising edge of DQS...missing the data on the falling edge.   http://www.alteraforum.com/forum/attachment.php?attachmentid=12962&stc=1   What is the correct set of components to perform this?

[Altera_Forum]

Hi,  

 I think there is no data in dataout_l because on this path there is aditional latch which is enabled from inclock high level. So in your case data at falling edge of inclock is registered but not passed trough latch. Give it another inclock pulse and you will see data on dataout_l port. If you read ALTDDIO_BIDIR IP Core user guide you will found out how ALTDDIO_BIDIR is implemented in device and timing waveforms.   Regards

[Altera_Forum]

Okay, that seems like the culprit. Unfortunately I don't control the inclock (DQS is driven from external device during reads), so I can't give it another clock. Are there any other options for making this scheme work? Sure someone has interfaced with a DDR memory controller?

[Altera_Forum]

Turns out all I had to do was invert the DQS signal.

[Altera_Forum]

Hi, 

 Why do you want your own controller? There is complete altera IP cores for DDR2 and DDR3 memory.

[Altera_Forum]

This is DDR[1]. Plus it's good to know in case there is a similar device interface, but not necessarily a DDR controller.