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declaring global objects is a SystemVerilog feature?

Altera_Forum
Honored Contributor II
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Hello, 

 

I'm quite new to FPGA design, and the Altera tools. I'm trying to work with a dev kit called the MotionFire, which contains a Cyclone III. When working with kits, the first step for me is typically to get the build environment up and running, and to re-program the device with the provided source. It looks like the MotionFire was made to be built with Quartus 8.1, and perhaps that's why I get this error when trying t compile the design source: 

 

Error (10839): Verilog HDL error at eth_avalon_functions.v(17): declaring global objects is a SystemVerilog feature 

 

I just don't know enough about Quartus or verilog to know what to do about this. What is SystemVerilog as opposed to just plain Verilog? Why is the presence of a SystemVerilog feature a fatal compilation error? Does anyone else have a MotionFire kit, or has anyone else encountered this error before? I'm fairly sure that I've set up the project according to the instructions (i.e. imported all required libraries and used SOPC builder to generate necessary design files). Maybe Quartus 9.1 (the verison I'm using) defaults to some setting that decides to hate SystemVerilog. 

 

 

Thanks for any help.
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Altera_Forum
Honored Contributor II
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Could be a bug in Quartus 9.1. 

Try a newer versions of Quartus, if possible. 

 

Or maybe it's an issue with the project settings. 

In Analysis & Synthesis settings for Verilog, check what flavor of Verilog is set as default.
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Altera_Forum
Honored Contributor II
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i don't think System Verilog is default yet, so try changing your QII project settings

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