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Valued Contributor III
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delay generation problem

hi, 

i have done a vhdl project with quartus and call it with nios, 

I don't have good result do to a delay generation. 

please how can i repair my work and have this result after this delay?? 

thank you
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Valued Contributor III
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Your problem description isn't very clear. If your VHDL component needs some time to process a request, you can have a status register with a "busy" or a "done" flag to tell the software to wait.

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Valued Contributor III
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Hi Daixiwen, 

can you tell me how to add this register?? If you have an example it will be wonderful and thank you very match.
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Valued Contributor III
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It depends on how you made your component. Show us your code and it will be easier to help you.

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Valued Contributor III
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ok this is my code: 

 

ENTITY comp IS 

PORT 

a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 

result : OUT STD_LOGIC 

); 

END comp ; 

ARCHITECTURE SYN OF comp IS 

begin 

process (a) 

begin 

if a=25 then result <= '1'; 

else result <= '0'; 

end if; 

end process; 

END SYN;
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Valued Contributor III
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okay, now what do you want to do and where do you need to have a delay?

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