hi,i have done a vhdl project with quartus and call it with nios, I don't have good result do to a delay generation. please how can i repair my work and have this result after this delay?? thank you
Your problem description isn't very clear. If your VHDL component needs some time to process a request, you can have a status register with a "busy" or a "done" flag to tell the software to wait.
ok this is my code:ENTITY comp IS PORT ( a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); result : OUT STD_LOGIC ); END comp ; ARCHITECTURE SYN OF comp IS begin process (a) begin if a=25 then result <= '1'; else result <= '0'; end if; end process; END SYN;