Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21323 Discussions

deleting logic increases macrocells?

Niko3
New Contributor I
‎03-13-2025 08:48 AM
95 Views

Hi,

I have a very curious effect:

The design of my project is a schematic for an EPM3064ATC100. After compilation 51 macrocells from 64 available ones are used. When I remove an AND with 4 inputs and a NAND with 2 inputs 64 macrocells are used - an increase of 13 macrocells!

What happened?

I'd like to know if this is normal?

Labels (1)
Labels:
0 Kudos

Link Copied

1 Reply
Niko3
New Contributor I
‎03-13-2025 08:58 AM
89 Views

Sorry, I changed a little bit more:

I additionally replaced an output by an input.

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.