demodulator with altera megafunction

[Altera_Forum]

hi, 

i've to realize a i-q demodulator for low frequencies signals with the classical scheme  https://www.alteraforum.com/forum/attachment.php?attachmentid=9034   The input signal is a 1,3Hz am modulated with a 50hz frequency for a logic HIGH.  now i want to understand some things...  1) the rate of the samples of input signal must be the same of the rate of the samples of sine and cosine output from NCO in order to perform multiplication... is it right? For example if the input signal is sampled with a 1khz clock i have to use the same clock for the NCO...is it right?  2)What about the FIR megafunction? Which clock signal have i to use? What is the best way (parameters, ecc..) for a low pass filter with fcutoff at 10Hz and a 60 db attenuation for 100Hz? Could you give me some advise on realization of the fir filter?  Thanks.

[Altera_Forum]

yes both NCO and filter should run at same speed. 

assuming your sampling rate is 1KHz, cutoff of 10Hz,attenuation of 60dB at 100Hz then  a possible filter is (in matlab) h = fir1(74,.02); you will need two such filters for each of I and Q

[Altera_Forum]

how did you find n and Wn of FIR1 matlab function? 

Thanks

[Altera_Forum]

--- Quote Start ---  how did you find n and Wn of FIR1 matlab function? Thanks  --- Quote End ---    cut off = 10Hz on a sampling frequency of 1KHz i.e. cutoff is 10/1000 relative to Fs of 1(1 cycle or 2pi) hence 10/1000 *2(pi) = 20/1000 pi = .02 pi  n is experimental to get -60dB, you can use other options...  apply freqz to see: freqz(h,1,0:.01:500,1000);

[Altera_Forum]

looks like you are inputting at fast clock rate. what is your clock rate. This should either match sample rate of your signal or use enable (on valid in) to get that rate.

[Altera_Forum]

As you easily see, either the test signal frequency or the filter sampling rate is incorrect because the number of samples per signal period is quite different from intended value. You don't show your HDL design so we can't know why. May be a problem with the source and sink handshake signals.

[Altera_Forum]

at the moment i've not written vhdl code yet... i'm using simulink and dsp builder by altera that allows the use of megafunctions as simulink blocks... i don't know how use clock signal in this enviroment

[Altera_Forum]

dspbuilder should have separate entries for system clock and sampling rate. Your clock frequency I assume will be higher than sampling rate in which case you let the filter see the correct rate through sink valid which should be at your input rate.