Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

error in quartus

Altera_Forum
Honored Contributor II
1,856 Views

Hey guys! :) 

 

when i run the code from https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios... in quartus 13.0sp1 and i got error and shown below. im using de1-soc board for my project. 

please help me:( 

 

 

Error (12006): Node instance "eth_std_main_system_inst" instantiates undefined entity "eth_std_main_system" 

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 3 warnings 

Error: Peak virtual memory: 593 megabytes 

Error: Processing ended: Fri Apr 28 17:23:26 2017 

Error: Elapsed time: 00:00:14 

Error: Total CPU time (on all processors): 00:00:10 

Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 3 warnings
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1 Reply
Altera_Forum
Honored Contributor II
837 Views

Readme says 

 

--- Quote Start ---  

To build the system, you will need to generate the system in SOPC Builder and compile the design in Quartus. 

--- Quote End ---  

 

You apparently skipped the first step.
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