fractional pll

[ESama]

Hello

I use a fractional pll in a cyclone 10 GX (10CX105YF672E5G) in order to generate a 100.000001 MHz from a 500 MHz. 

Every thing is working well when the 500 MHz input frequency is present before the fpga is powered on but the fpll doesn't lock if the input frequency is provided after the fpga has been powered.

But in practice, I m not able to provide the input frequency at startup.

My question is: how could I lock the fpll in that case?  

Very best regards

Etienne

[ESama]

Hello

I finally found that a recalibration process of the fpll was required in that case.

I have just implemented that recalibration and it works fine.

Regards

Etienne

[AqidAyman_Intel]

Hi Etienne,

I really glad your issue is resolved and your willingness to share with us the steps taken to resolve the issue.

With that, I wish to follow up with you. Is there any other help needed?

Regards,

Aqid