general question regarding Signal TAP

[Altera_Forum]

Hello I have some general questions regarding Signal Tap. 

 1.) When I add nodes to watch them. Is it the best (or usual) way to click on "Trigger enable" on EVERY node and set the trigger conditions to "DONT-CARE" ? Has this way some disadvantages ? What I want to avoid is to recompile the design, when I change a trigger condition or change on of the signals I want to watch. Its clear for me that I have to recompile when I add a node but when I change one of my signal I 've already added to my nodes I dont want to recompile    2) Trigger clock: Which kind of clock should I use for the trigger clock?  a) one of the clocks where data are captured or  b) one extra PLL output with a maximum frequency(~300 MHz - 500 Mhz)which is only used for the trigger clock in Signal Tap. I am not sure but with method b) I have the feeling that things are sometimes not working well

[Altera_Forum]

1) You would use usually enable all signals for trigger, if any of them is a meaningful trigger candidate. Resource economy and timing constraints with critical design can be a reason to use only selected signals. 

 2) The acquisition clock would be the system clock in most cases. It should be synchronous to your design under test at least, may an integer multiple of the system clock, but most likely not above 100 or 200 MHz, because timing closure becomes rather difficult then.  Consider, that Quartus try to achieve timing closure for the SignalTap design part as it does for the rest of it. It it doesn't succeed, also failure of other design parts may occur. Timing violations show in SignalTap often as waveform artefacts.  Before Altera introduces the Storage Qualifier feature, it has been often necessary to us e a divided clock for long time-scale acquisitions, although it caused timing violations. Now, you can use divided clocks and similar as qualifier and keep all timing constraints.

[Altera_Forum]

Thanks for the quick answer.... 

by the way I also come from Bochum :)