i am trying to use global parameter. i get an error for simple module.
Error (10170): Verilog HDL syntax error at para.v(15) near text ";"; expecting "]"
module para (clk, d, ena, q);
input clk;
input [7:0] d;
output reg [7:0] q;
reg [5:0] variable;
`define a 6;
always @ (posedge clk)
begin
variable = `a;
for (i=0; i<8; i=i+1)
begin
q[i] <= d[`a-variable]; // error
variable = variable -1;
end
end
endmodule
However, previously i did the almost the same(attachment:bold font) without error. The different is quartus II version and application.
How to solve the error?
thanks
