hello sir can u help me, i am displaying 3 digits using seven segment display, everything is done i got output(used verilog HDL code) but the problem is during power up it is reset to "000". previous values are not stored. so what is the solution

[Tricky]

FPGAs are volatile, so state is always lost on reset

[CShek1]

k thank you for reply, but what is the solution sir.,

[Tricky]

What are you trying to do? Why do you need to retain state after power down?​