- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Link Copied
5 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
A general note(I have no idea what modules you have in hand): The parallel mpeg TS inteface must include video data(8 bits), clock and data_valid. The ASI generator needs all above signals and converts video_data to a serial stream(without clk or data_valid) and uses 8b/10b encoding. The clk has to be recovered by ASI Rx device from data stream. The data_valid is implied through null character insertion, the Rx has to ignore these null characters. Your description of mpeg packet structure and system level diagram has nothing to do with TS signals interface. Documents often don't show low level details except at relevant diagrams.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
thanks for your reply,
can you send me the datasheet of The parallel mpeg TS inteface to understand how does it work?- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
and other little question
wa know that the type of output signal for asi-tx is "dvb asi mpeg ts", and what about the type of the input( 8bit parallel data)? is it called MPEG SPI TS????- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The video interfacing standards are set by ETSI(for European DVB). If you search ETSI site you will find them but the parallel interface is too obvious anyway, just 8 bits data plus clk plus data_valid. It is indeed called SPI = synchronous Parallel Interface as opposed to the more involved ASI(Asynchrnous Serial Interface). There is also SSI(Synchronous Serial Interface) but don't know if anybody uses it.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
thanks for your reply,
can you send me the datasheet or the IP core of The parallel mpeg TS inteface which generating those signals ( video data(8 bits), clock and data_valid. ) to understand exactly how does it work(specially the file .bsf)?
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page