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Altera_Forum
Honored Contributor I
9,843 Views

help for audio codec using VHDL

i am a begineer at using altera DE2 board and VHDL. i have to complete my project with in 10 days time but dont have any idea of where to start and how.. help ......... 

i need to build a duplex audio system that works similar to a phone but here CDMA must be considered.  

first i would like to have some good advice on where to start and how .... on audio CODEC  

any help would be more than appreciated
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72 Replies
Altera_Forum
Honored Contributor I
310 Views

Have you looked on opencores.org?

Altera_Forum
Honored Contributor I
310 Views

nope i didnt find anything there i just need codes to get audio from the audio input port and then output it thourh the other audio playing port in VHDL

Altera_Forum
Honored Contributor I
310 Views

 

--- Quote Start ---  

i am a begineer at using altera DE2 board and VHDL. i have to complete my project with in 10 days time but dont have any idea of where to start and how.. help ......... 

i need to build a duplex audio system that works similar to a phone but here CDMA must be considered.  

first i would like to have some good advice on where to start and how .... on audio CODEC  

any help would be more than appreciated 

--- Quote End ---  

 

 

I have attached a few pieces of my hardware description in VHDL. Note that is for the Wolfson WM8731 on the DE1 board. But the DE2 has the same chip so the attached hardware description should work with the appropriate pin assignment modifications. 

 

Note that I could not upload clockBuffer.vhd because of the 5 file limit. BUT you should be able to easily create the clockBuffer using the MegaIP wizard. Also I do not claim my code is the best (especially the i2c part) but it does the job. 

 

You should go through the code and understand how it works. Honestly, if you are a beginner with VHDL and DE2, it may be very difficult to finish this project in 10 days (unless you have previous hardware design experience). 

 

Good luck. 

 

Bart
Altera_Forum
Honored Contributor I
310 Views

would you please upload it with the whole project .... that would be of great help... please zip all the project file and upload it........... that would be helpful... anyways than you for your update

Altera_Forum
Honored Contributor I
310 Views

 

--- Quote Start ---  

would you please upload it with the whole project .... that would be of great help... please zip all the project file and upload it........... that would be helpful... anyways than you for your update 

--- Quote End ---  

 

 

Hey, 

 

My project will not help you because I don't have a DE2 board (yet). Anyway, I have attached the final .vhd file (clockBuffer). You should simply be able to create a new Quartus project, import pin assignments for the DE2 and modify the top-level accordingly. 

 

Again IMO, if you have difficulty migrating my project from the DE1 to DE2 board, finishing a CDMA design in 10 days might be very difficult. 

 

Bart
Altera_Forum
Honored Contributor I
310 Views

this is the pin table i just cant find the right pin for the names you have defined........ the board keeps playing sound irrespective of the program..... i dont know what to do ........ even if i get this done it would be great achievement leave alone the CDMA part.... i might use HDLC frame format instead but currently i need to manipulate the audio input. ...... and since the system is to be full duplex using nios is not the solution...... would you help me in pin assignment .............that would of great help  

cheers  

thanks again for replying
Altera_Forum
Honored Contributor I
310 Views

i tried it with your program it just gives a silent output i couldnt get the mic in output using it can you suggest why is that happening???

Altera_Forum
Honored Contributor I
310 Views

 

--- Quote Start ---  

i tried it with your program it just gives a silent output i couldnt get the mic in output using it can you suggest why is that happening??? 

--- Quote End ---  

 

 

The comments at the beginning of my top-level says that my hardware does only Line-In to Line-Out loopback.  

 

If you want to use the Mic, then you have to modify the i2c initialization routine. It is actually simple to do. Read the audio codec datasheet (it should be on your DE2 CD), specifically starting at page 46 where it describes the register map. Figure out the exact register you need to program for mic in. 

 

Good luck. 

 

Bart
Altera_Forum
Honored Contributor I
310 Views

The code should be published at the Altera Wiki. It's much more instructive than the respective Terasic demonstration projects.

Altera_Forum
Honored Contributor I
310 Views

 

--- Quote Start ---  

The code should be published at the Altera Wiki. It's much more instructive than the respective Terasic demonstration projects. 

--- Quote End ---  

 

 

Thanks for the tip. I am creating a website which will have reference designs from our school and was going to post a link to it on these forums. But, I will publish this code and others at Altera wiki as well (once I have cleaned them up a bit). 

 

Have a great week. 

 

Bart
Altera_Forum
Honored Contributor I
310 Views

thank you again i have now been able to configure the mic in line in and out ............. sorry to bother you again but i want another help how do i use the data of mic in.......... in your program i can use ta line in data but how to use the mic in data???

Altera_Forum
Honored Contributor I
310 Views

well i have been able to find the sloution thank you ......... now i am going for CDMA ............

Altera_Forum
Honored Contributor I
310 Views

Hello, 

 

I have tried to replicate the project from mbharat. 

But I always get errors like: 

Error: Port "acknowledge" does not exist in macrofunction "i2cController" 

(same with done, i2c_scl, i2c_sda, readWriteEnable and start) 

 

Do I have the wrong I2C_Controller.v? 

 

Edit: I also have the DE1 board.
Altera_Forum
Honored Contributor I
310 Views

 

--- Quote Start ---  

Hello, 

 

I have tried to replicate the project from mbharat. 

But I always get errors like: 

Error: Port "acknowledge" does not exist in macrofunction "i2cController" 

(same with done, i2c_scl, i2c_sda, readWriteEnable and start) 

 

Do I have the wrong I2C_Controller.v? 

 

Edit: I also have the DE1 board. 

--- Quote End ---  

 

 

I didn't post a .v file, my hardware is described using VHDL. Thanks. 

 

Bart
Altera_Forum
Honored Contributor I
310 Views

thanks for the fast reply, 

 

I know that you dont posted a v. file, but I only have the i2c controller from the demonstrations of altera. 

 

I do not know where I can get an appropriate VHDL. 

To rewirte the existing .v to .vhd I understand not much enough verilog.
Altera_Forum
Honored Contributor I
310 Views

 

--- Quote Start ---  

thanks for the fast reply, 

 

I know that you dont posted a v. file, but I only have the i2c controller from the demonstrations of altera. 

 

I do not know where I can get an appropriate VHDL. 

To rewirte the existing .v to .vhd I understand not much enough verilog. 

--- Quote End ---  

 

 

Oh, I think I understand: your tried to port Terasic's audio codec verilog source to VHDL?  

 

To answer your question about appropriate VHDL, I had earlier posted in this thread my .VHDL audio codec interface. You can first just try to synthesize that and see if it works. Then you should go about reading the audio codec datasheet and try to understand the VHDL I posted. Mind you my i2c controller is not the best, I am working on an updated version. I will post that as soon as I am done. 

 

Second, as far as Terasic's audio codec verilog is concerned, I just resynthesized their HDL (from /DE1_CD_v0.8/DE1_i2sound/) on version 10.0 of Quartus. It synthesized fine, I didn't get any errors. 

 

Bart
Altera_Forum
Honored Contributor I
310 Views

as someone pointed out, the code is very clear and I think really useful. 

I've managed to use it with an i2c controller ported from altera's one, and the waveform generation just works fine. if i try loopback i have this result (with signal on line in): 

sw0+sw9 up: hex0 stuck on "5", static. every time i switch sw0 down and then up, static (volume varying between trials). 

 

basically, board now adds static to signal input, if present, or just plays static if no signal input is present. any hints? am I missing something? 

 

thank you in advance,  

best regards 

 

C
Altera_Forum
Honored Contributor I
310 Views

It's the same with me too. 

But again in brief. 

sw0 on & (sw8 sw9) off -> sine wave 

sw0 on & sw9 off & sw8 on -> square wave 

it is up to here is the same as in the comments:) 

 

sw0 on & sw9 on & sw8 off -> adc-dac-loopback + noise 

 

 

But mbharat will publish his code when he has once again revised. 

Stay tuned :) .
Altera_Forum
Honored Contributor I
310 Views

Hey, 

 

@carlo.bono: I believe my master FSM is designed to go through the initialization routine only once and get to a "stop" state. Hence you see a "5" (or "S" :D) on HEX0 where I output the current state of the master FSM. However the static is a more serious issue. But you say that you have a new i2c routine? However if your waveform generation works fine, why do you say the board adds static if no signal input is present? I am wondering if my interface to the data registers has issues with the new i2c routine. 

 

@ moou: Thanks for the vote of confidence, it will be another couple of weeks before I can get all the information up. I am designing a website that will incorporate all the course materials we have for digital systems at the Milwaukee School of Engineering (where I am an assistant prof.). This should include stuff on basic concepts, VGA, audio, NIOS, student projects etc. but all targeted for the DE1. 

 

I will post a link on the Altera wiki once this is done but it is taking me a while because of all the material I have to organize. But it should be done in a couple of weeks. 

 

Bart
Altera_Forum
Honored Contributor I
84 Views

first thank you for your replies. 

 

i tried both a ported version and the original verilog i2c controller (as your audio_codec_controller requests ans i2c_controller component). 

 

during lunch break i made a new project and i was not able to reproduce "varying static". but static is still present when sw1&9 are up (adc dac loopback), as moou pointed out, with or without input signal on line in - i've tried different i/o audio sources and the problem persists. 

 

initialization works fine as expected (5 on hex0) and sine/square wave generation works well too. 

 

maybe i'm missing some macroscopic point. anyways thank you for your help. 

best regards 

cb
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