help needed!!!

[Altera_Forum]

I am trying to do my assignment, I got this error in my port map 

Error (10500): VHDL syntax error at FA.vhd(34) near text "port"; expecting "(", or "'", or "." Error (10500): VHDL syntax error at babi3.vhd(38) near text ")"; expecting "<="this my program...the error is in my port map??? I am newbie in Quartus...help me plz...:confused::confused::confused::confused:  library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity DU is port( clk,rst : in std_logic; dataA,dataB : in std_logic_vector(31 downto 0); Psel,Qsel,Rsel,Tsel : in std_logic_vector(1 downto 0); Use1,Wsel : in std_logic_vector(2 downto 0); ldA,ldB,ldE1,ldE2,ldM1,ldM2,ctrlM1,ctrlM2,ldP,ldQ: in std_logic; A_tp,B_tp : out std_logic_vector(31 downto 0); E1_tp,E2_tp,P,eq,lt : out std_logic_vector(7 downto 0); M1_tp,M2_tp,Q : out std_logic_vector(21 downto 0) ); end DU; architecture DU_arch of DU is signal Ain,Bin :std_logic_vector(31 downto 0); signal E1in,E2in :std_logic_vector(7 downto 0); signal M1in,M2in :std_logic_vector(21 downto 0); signal zero1 :std_logic; signal Pin :std_logic_vector(7 downto 0); signal Qin :std_logic_vector(21 downto 0); component RegE1 port( d : in std_logic_vector(7 downto 0); en,clk,rst : in std_logic; q : buffer std_logic_vector(7 downto 0)); end component; component RegE2 port( d : in std_logic_vector(7 downto 0); en,clk,rst : in std_logic; q : buffer std_logic_vector(7 downto 0)); end component; component RegA port( d : in std_logic_vector(31 downto 0); en,clk,rst : in std_logic; q : buffer std_logic_vector(31 downto 0)); end component; component RegB port( d : in std_logic_vector(31 downto 0); en,clk,rst : in std_logic; q : buffer std_logic_vector(31 downto 0)); end component; component RegM1 port( d : in std_logic_vector(21 downto 0); ldsh,en,w,clk,rst : in std_logic; q : buffer std_logic_vector(21 downto 0)); end component; component RegM2 port( d : in std_logic_vector(21 downto 0); ldsh,en,w,clk,rst : in std_logic; q : buffer std_logic_vector(21 downto 0)); end component; begin zero1 <= '0'; RegA port map( dataA,ldA,clk,rst,Ain); RegB port map( dataB,ldB,clk,rst,Bin); RegE1 port map( E1in,ldE1,clk,rst,E1_out); RegE2 port map( E2in,ldE1,clk,rst,E2_out); RegM1 port map( M1in,ctrlM1,ldM1,zero1,clk,rst,M1_out); RegM2 port map( M2in,ctrlM1,ldM1,zero1,clk,rst,M2_out); RegP port map( Pin,ldP,clk,rst,P); RegQ port map( Qin,ldQ,zclk,rst,Q);

[Altera_Forum]

try component RegE1 is port(and do the same for all your component declarations.

[Altera_Forum]

The is keyword in component declaration is optional. As said, the error is in component instantiation. It simply misses instance names. 

regainst: RegA port map( dataA,ldA,clk,rst,Ain);

[Altera_Forum]

--- Quote Start ---  The is keyword in component declaration is optional. As said, the error is in component instantiation. It simply misses instance names. regainst: RegA port map( dataA,ldA,clk,rst,Ain);  --- Quote End ---    Istance names missing is one of the errors. Ports declaration are also needed to be added. The fellowing information is I got after adding instance names. I think checking several times after constructing programme could greatly avoid those errors. ** Error: E:/modelsim_prog/du.vhd(69): (vcom-1136) Unknown identifier "e1_out". ** Error: E:/modelsim_prog/du.vhd(70): (vcom-1136) Unknown identifier "e2_out". ** Error: E:/modelsim_prog/du.vhd(71): (vcom-1136) Unknown identifier "m1_out". ** Error: E:/modelsim_prog/du.vhd(72): (vcom-1136) Unknown identifier "m2_out".Good Luck!  Salming