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Valued Contributor III
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hold time violation using MAX V

Hi, 

 

I saw some hold time violation when I trying to run the STA. 

I believe the problem is because the source and destination FFs of this path are on different clock domains, and the tool thinks there is large skew between these domains. skew= 5.42, data delay = 3.17, the slack is around -2.3. 

so is there anything I can do to fix this problem? 

 

Thanks!!!!
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Valued Contributor III
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If the clock domains are asynchronous (no frequency or phase relationship) you need a false path timing exception in your .sdc file (set_false_path or set_clock_groups). If the domains are synchronous to each other, you need a multicycle timing exception.

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Valued Contributor III
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--- Quote Start ---  

If the clock domains are asynchronous (no frequency or phase relationship) you need a false path timing exception in your .sdc file (set_false_path or set_clock_groups). If the domains are synchronous to each other, you need a multicycle timing exception. 

--- Quote End ---  

 

 

The suggestion sounds ambiguous to me. You'll first determine how data can be consistently transferred between both clock domains and design the logic respectively. Then specify appropriate clock constraints. The suggested constraints might fit under circumstances.
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Valued Contributor III
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--- Quote Start ---  

Hi, 

 

I saw some hold time violation when I trying to run the STA. 

I believe the problem is because the source and destination FFs of this path are on different clock domains, and the tool thinks there is large skew between these domains. skew= 5.42, data delay = 3.17, the slack is around -2.3. 

so is there anything I can do to fix this problem? 

 

Thanks!!!! 

--- Quote End ---  

 

 

How are the two clocks related? Are they the same frerquency, different phases? Or different frequencies? Derived from same source, or different input sources? 

 

If you know enough about the relationship of the clock waveforms you should be able to setup timing relationships for the data transfer (setup, hold, multicycle). 

 

Otherwise if the sources are asynchronous you will need to setup a false timing path to remove the timing check (and implement the appropriate synchronizer logic as well).
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Valued Contributor III
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Hi, 

the output clock is half frequency of input clock. output clock(100ns), input clock(50ns). 

when I run RTL simulation, everything looks good. 

 

however, when I trying to run gate level simulation, the output clock always shift half clock period to the left. 

 

I have set multicycle exception for these two clock,the output clock always delay one input clock period . 

set_multicycle_path 1 -setup -start -from CLK -to CLK2 

set_multicycle_path 0 -hold -start -from CLK -to CLK2 

 

I not sure what the problem is.  

 

Thanks!
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Highlighted
Valued Contributor III
9 Views

 

--- Quote Start ---  

How are the two clocks related? Are they the same frerquency, different phases? Or different frequencies? Derived from same source, or different input sources? 

 

If you know enough about the relationship of the clock waveforms you should be able to setup timing relationships for the data transfer (setup, hold, multicycle). 

 

Otherwise if the sources are asynchronous you will need to setup a false timing path to remove the timing check (and implement the appropriate synchronizer logic as well). 

--- Quote End ---  

 

 

Hi, 

the output clock is half frequency of input clock. output clock(100ns), input clock(50ns). 

when I run RTL simulation, everything looks good. 

 

however, when I trying to run gate level simulation, the output clock always delay one input clock period . 

 

I have set multicycle exception for these two clock, but still see the shift. 

set_multicycle_path 1 -setup -start -from CLK -to CLK2 

set_multicycle_path 0 -hold -start -from CLK -to CLK2 

 

I not sure what the problem is.  

 

Thanks!
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Highlighted
Valued Contributor III
9 Views

 

--- Quote Start ---  

Hi, 

the output clock is half frequency of input clock. output clock(100ns), input clock(50ns). 

when I run RTL simulation, everything looks good. 

 

however, when I trying to run gate level simulation, the output clock always delay one input clock period . 

 

I have set multicycle exception for these two clock, but still see the shift. 

set_multicycle_path 1 -setup -start -from CLK -to CLK2 

set_multicycle_path 0 -hold -start -from CLK -to CLK2 

 

I not sure what the problem is.  

 

Thanks! 

--- Quote End ---  

 

 

So output clock is input clock divided by two. Do you use a PLL to generate the output clock, or just a FF as a divider? 

 

Do you use sdc commands create_clock and / or create_generated_clock, or derive_pll_clocks (if using pll). Can you show the sdc commands you use?
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Valued Contributor III
9 Views

 

--- Quote Start ---  

So output clock is input clock divided by two. Do you use a PLL to generate the output clock, or just a FF as a divider? 

 

Do you use sdc commands create_clock and / or create_generated_clock, or derive_pll_clocks (if using pll). Can you show the sdc commands you use? 

--- Quote End ---  

 

 

Hi ak6dn, 

Thanks so much for your help! 

I just use a FF as a divider, i'm not using the pll to create the output clock, please see below verilog code. 

 

always @(posedge clk or negedge reset)  

begin 

if (!reset)  

two_clkout <= 0;  

else 

two_clkout <= ~two_clkout; 

 

end 

 

and  

 

sdc comment: 

create_clock -name {clk} -period 50.000 -waveform { 0.000 25.000 } [get_ports {clk}] 

 

do I need to put the create_generated_clock for the output clock into the sdc file,even though I just use a FF divider? 

 

Thanks a lot!
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Valued Contributor III
9 Views

 

--- Quote Start ---  

Hi ak6dn, 

Thanks so much for your help! 

I just use a FF as a divider, i'm not using the pll to create the output clock, please see below verilog code. 

 

always @(posedge clk or negedge reset)  

begin 

if (!reset)  

two_clkout <= 0;  

else 

two_clkout <= ~two_clkout; 

 

end 

 

and  

 

sdc comment: 

create_clock -name {clk} -period 50.000 -waveform { 0.000 25.000 } [get_ports {clk}] 

 

do I need to put the create_generated_clock for the output clock into the sdc file,even though I just use a FF divider? 

 

Thanks a lot! 

--- Quote End ---  

 

 

Yes, unless Quartus detects that FF output as a clock (from your description of the problem however it appears not to). 

 

I would use something like: create_generated_clock -name two_clkout -multiply_by 2 -source [get_ports {clk}] [get_registers {two_clkout}] 

 

and then validate in your DESIGN.sta.rpt file in the CLOCKs table that it appears as it is supposed to as a clock.
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Valued Contributor III
9 Views

 

--- Quote Start ---  

Yes, unless Quartus detects that FF output as a clock (from your description of the problem however it appears not to). 

 

I would use something like: create_generated_clock -name two_clkout -multiply_by 2 -source [get_ports {clk}] [get_registers {two_clkout}] 

 

and then validate in your DESIGN.sta.rpt file in the CLOCKs table that it appears as it is supposed to as a clock. 

--- Quote End ---  

 

 

Thanks!! 

BUt when I put the clock create_generated_clock, the Quartus tool shows two clocks, one is the output clock (two_clkout) another one is two_clkout~reg0, and it ask me to constrain the two_clkout~reg0. 

when I do the RTL simulation, the two_clkout is generated right after the reset signal. 

When I do the gate level simulation, the two_clkout is delayed by one input clock cycle. 

 

I'm not sure why it happens.
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Valued Contributor III
9 Views

A false path exception is required on the output clock. Otherwise, the tool still analyzes it as an unconstrained output data path.

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Valued Contributor III
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For future reference: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_timequest_cook... 

 

Pages 1~8 for clock generation references, pages 3~4 particular for divide-by-N clocks using registers.
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Valued Contributor III
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Hi guys, 

Thanks a lot of for your help, the problem was fixed!!!
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