how to design the system using SSRAM CY7C1470V33 in the sopc builder

[Altera_Forum]

HI  

we are using the SSRAM CY7C1470V33 in our design (instead of CY7C1380C which is part of the SOPC builder). How do we go about designing the system . Please help us regards, Bhandari

[Altera_Forum]

You can simply write a simple tcl file which defines your component parameters. 

I attached a sample. Change the required parameters and possibly the name to match your sram and copy the file into the altera\<your version>\ip\user_components directory. If you change the file name, keep the _hw.tcl suffix, otherwise sopc builder will not find it. When you refresh the component list in sopc builder, you should find the new sram component in the sram section  Regards Cris

[Altera_Forum]

How do I edit the file so that it is compatible with SRAM 512kb on de2 board?

[Altera_Forum]

I have the same quastion. What to do to connect sram on de2 controller to nios2?

[Altera_Forum]

--- Quote Start ---  How do I edit the file so that it is compatible with SRAM 512kb on de2 board?  --- Quote End ---    You must change what is needed to meet your system specification. If bus width already matches, you mainly must only adjust wait states so that they comply with your sram speed (you must refer to sram datasheet). Then you possibly want to change component name or other parameters.

[Altera_Forum]

how to open the tcl file? i use open using notepad..

[Altera_Forum]

Notepad or any editor. It's a simple text file. 

For a 512k sram you'll need to change at least add_interface_port avalon_tristate_slave addr address Input 19 (I used 16 because a simply had a 64kB device) You can initially mantain unchanged the other parameters. Probably this is enough for your first tests with CY7C1470V33. You can then adjust wait cycles to improve access time performance.  Regards

[Altera_Forum]

hi, but i am not using CY7C1470V33. mine is IS61LV25616 which is 512KB.

[Altera_Forum]

Hello 

 I have same problem with connectiong sram and flash. I added flash and sram 256x16. Flash from SOPC library and sram with my new component. In sopc project I have 2 address spaces: one for flash and one for sram but I have one space for data: 16 bits. Sram have 16 bit data bus and flash 8 bits. How can I connect flash and sram to one 16 bits bus? Can I split those data buses?

[Altera_Forum]

what is the model of your SRAM?

[Altera_Forum]

Is61wy256168ll

[Altera_Forum]

hmm... different from mine

[Altera_Forum]

I think this should be similar to mine. Where do you have problem with running yours?

[Altera_Forum]

--- Quote Start ---  You can simply write a simple TCL file, which defines the component parameters.  --- Quote End ---    Yes i have the TCL file for SRAM for de2 board. when i send my code to board using programmer, weird is, suppose all light on board should be off, but one of the light on 7-seg-dis is on. do you know why? pls see attachment.

[Altera_Forum]

Sorry for another dumb question from a newbie, but do I have to drive the custom SRAM through an Avalon-MM tristate buffer? I really wish there was a really simple example design for this kind of stuff as my search of the literature always gets to some dead-end docs that don't tell me how to use SRAM.

[Altera_Forum]

To answer my own question, experimentation shows that defining an SRAM in a _hw.tcl file and connecting it via an Avalon-MM tristate buffer seems to work!

[Altera_Forum]

This component doesn't work with QSys. Apparently anything using an Avalon MM tri-state buffer needs an upgrade. 

It ask you to perform the upgrade, which i do and it doesn't change anything.   Any ideas?

[Altera_Forum]

--- Quote Start ---  This component doesn't work with QSys. Apparently anything using an Avalon MM tri-state buffer needs an upgrade.  It ask you to perform the upgrade, which i do and it doesn't change anything.   --- Quote End ---   QSys has a few extra features compared to SOPC. Check if the upgraded component defines all the required interfaces and if all ports are correctly connected. Also check the base address: I can't remember right now if your SRAM component must be assigned to an absolute address or offset from TS bridge. For more help you must specify what your problem exactly is: can't build Qsys? SRAM doesn't work at all? you can access SRAM, but you get data errors?