I'm implementing a mathematical operation in Quartus using ALTERA_FP_FUNCTIONS, the input signal is coming from the ADC through low frequency generator.
To interface with the DAC TI 5672, I use IP core converter 14->32 bits float single precision, then i inverse the sign of the MSB to convert to complement two.
The question is:
As the DAC TI5672 has a limited output that cannot overpass 3.3 V, how can we fix that, to make a correspondance between the output of the IP Functions and the output range of the DAC ;
here belw is the interface of the DAC
ENTITY mlp IS
port (clk: in std_logic;
-- clock_out: out std_logic;
reset: in std_logic;
enable: in std_logic;
Data_in: in std_logic_vector(13 downto 0);
Data_out: out std_logic_vector (13 downto 0)
architecture mlp_arch of mlp is
signal count : std_logic_vector(13 downto 0);
--port map (
--clkin => clk ,
--rst => reset ,
if reset='1' then
elsif rising_edge(Clk) then
if enable='1' then
-- if count > '1'&'1'& x"FFF" then
-- Data_out <='0'&'1'& x"FFF";
--elsif count < '0'&'0'& x"000" then
-- Data_out<='1'&'0'& x"000";
Data_out(12 downto 0)<= count(12 downto 0);
Data_out (13) <= not count(13);
Apologize for the delay in response as the case was only re-routed today to me. Allow me some time to look into your issue. I shall come back to you with findings.
Thank you for your patience.
As I understand it, you seems to have some inquiries related to IO voltage at the interface between DAC TI5672 and FPGA devices. I understand that you specific inquiry is as following:
"As the DAC TI5672 has a limited output that cannot overpass 3.3 V, how can we fix that, to make a correspondence between the output of the IP Functions and the output range of the DAC ;"
To ensure we are on the same page, just would like to check with you on the following:
1. What is the FPGA device that you are using currently?
2. I understand that the DAC's output is connecting to FPGA's input. You seems to mention about 3.3V. Sorry as I am not familiar with DAC TI5672. Would you mind to further elaborate on this 3.3V?
3. Just wonder if you are trying to say the DAC output voltage swing must be smaller than 3.3V. And what is the IO standard to use at the FPGA input?
4. Please feel free to correct my understanding if I am wrong. Sorry for the inconvenience.
Please let me know if there is any concern. Thank you.