how tooutput a high speed clock

[Altera_Forum]

I need a clock to control high speed AD.But I measure it with oscillograph finding it is very bad so that AD can't work. 

thank you very much

[Altera_Forum]

--- Quote Start ---  I need a clock to control high speed AD.But I measure it with oscillograph finding it is very bad so that AD can't work.  --- Quote End ---    What clock rate is your ADC?  The design documents here;  http://www.ovro.caltech.edu/~dwh/carma_board/  Discuss the design of a 1GHz ADC.  If you can provide more detail, I can offer suggestions.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  I need a clock to control high speed AD.But I measure it with oscillograph finding it is very bad so that AD can't work. thank you very much  --- Quote End ---   Bad in what sense? Is it due to incompatible voltage levels (for example ADC is expecting clock in LVPECL standard and FPGA is outputting 3.3V LVCMOS) or due to high clock jitter? Normally you would not want to clock high performance ADC from FPGA, because FPGA output clocks have relatively high jitter.

[Altera_Forum]

If I can't get high performance clock from FPGA,what should I do? I need change the ADC clock to control sampling rate(we are designing a digital storage osciioscope). I just need a 1M time Sampling clock and 200M Equivalent Sampling,so I need a clock from FPGA. I just change the ADC clock's frenquency to get different sampling rate.I don't know why FPGA output signal(a little high frenquency) is so bad.

[Altera_Forum]

FPGA IO signals can't be good or bad as such. They undergo the general rules of interfacing high speed digital signals. As you are talking about 1 MHz clock frequency, I guess, the problem may be, that you aren't familar with logic signals in the FPGA typical speed range. 

 A good standard to get clean square waves is using source side impedance matching. Presumed you have a cable or PCB trace with e.g 50 to 80 ohm characteristic impedance, supplement the FPGA pins output impedance with a series resistor to make the sum match the characteristic impedance. The method will work with a low to moderate capacitive load.  For a detailed discussion, you should tell more about the problem you're facing. Posting waveform photos isn't a bad idea.  P.S.: For high performance requirements, e.g. to achieve low jitter, it may be reasonable, to send the clock signal using the LVDS IO standard and place a LVDS receiver near the load. This will effectively eliminate most common mode interferences possibly present in a highly populated digital circuit.

[Altera_Forum]

I'm just a beginner and not familar with FPGA.My problem is that I don't how to deal with the signal of FPGA including input and output. I used a comparator to deal with the clock from FPGA.Is there other solution to deal with it. 

Thank you very much

[Altera_Forum]

--- Quote Start ---   I need change the ADC clock to control sampling rate(we are designing a digital storage osciioscope). I just need a 1M time Sampling clock and 200M Equivalent Sampling,so I need a clock from FPGA. I just change the ADC clock's frenquency to get different sampling rate.  --- Quote End ---  If you are designing an oscilloscope, then the number of bits in your ADC, and the highest sampling frequency determine your required jitter. For example, if your ADC is 12-bits, and the maximum frequency is 100MHz, then the maximum jitter (clock plus ADC) is   tj < 1/(2*pi*fmax*2^B ) = 1/(2*pi*100MHz*2^12) = 0.39ps  Which is a difficult specification to meet. You would generally use an external clock source (low jitter crystal or VCO) to implement such a clock.  Why do you want to implement an equivalent sampling scheme at 200MHz? This is a low enough frequency that you can implement a real-time sampling oscilloscope. There's no advantage in trying to achieve equivalent time sampling at this frequency, as you still need to meet the analog input bandwidth and jitter specification of a real-time sampling scope.  Cheers, Dave

[Altera_Forum]

Because I just have low speed ADC,but I need sample a high frenquency signal.But if I use an external clock to control ADC,how can I change the sampling rate. I'm confused! Thank you very much.

[Altera_Forum]

--- Quote Start ---  Because I just have low speed ADC,but I need sample a high frenquency signal.   --- Quote End ---  How do you know this ADC can sample a high-frequency signal? What is the analog input bandwidth of the ADC? Do you have a data sheet for the ADC? Please post a link.    --- Quote Start ---   But if I use an external clock to control ADC,how can I change the sampling rate.  --- Quote End ---  You can use an external clock source that is programmable.  However, its not clear that you understand how equivalent sampling (also known as repetitive interlaced sampling) works either. How do you think you can use a 1MHz ADC to sample at 200MHz?  Cheers, Dave

[Altera_Forum]

You can use an external clock source that is programmable. 

An external clock source that is programmable? Can you give a example(the chip's name )?  As you know,I am designing an oscilloscope so the sample rate Varies greatly. I design divider that is programmable using FPGA to control ADC clock.   Equivalent sampling is to use low-frequency sampling high-frequency signals.  I use the sequential sampling technique. sampling a point a cycle of signal, and delay a slight time(slight delay determines the sampling rate ). I use the 200M counting clock signalto get signal's period. And I design a state machine get the clock to control AD.

[Altera_Forum]

--- Quote Start ---  You can use an external clock source that is programmable.  An external clock source that is programmable? Can you give a example(the chip's name)?   --- Quote End ---  One option is to use a direct digital synthesizer (DDS). Analog devices has many devices.    --- Quote Start ---    As you know,I am designing an oscilloscope so the sample rate Varies greatly. I design divider that is programmable using FPGA to control ADC clock.     --- Quote End ---  The sample rate of the ADC does not have to vary at all. You can vary the sample rate once you have the data on the FPGA using multi-rate sampling and digital filtering. While this may seem more complex, it may in fact be simpler, in that your ADC operates at a fixed frequency. For example, I run my 1GHz ADCs at 1GHz all the time. Digital filters are then used to generate 250MHz, 125MHz, etc, down to 2MHz sampling modes.    --- Quote Start ---   Equivalent sampling is to use low-frequency sampling high-frequency signals.  I use the sequential sampling technique. sampling a point a cycle of signal, and delay a slight time(slight delay determines the sampling rate ). I use the 200M counting clock signalto get signal's period. And I design a state machine get the clock to control AD.  --- Quote End ---  Ok, glad to hear you understand how to make this work. However, this scheme will not work with any old 1MHz ADC. The 1MHz ADC must have an input analog bandwidth in excess of 100MHz and the ADC clock plus aperture jitter must meet the requirements I state above, or you must have a wide bandwidth track-and-hold (T/H) or sample-and-hold (S/H) in front of your ADC, with in excess of 100MHz of bandwidth clocked by a clock with the jitter requirements I state above.  You cannot avoid the input bandwidth requirement, and having a very clean clock source.  Why are you trying to use a 1MHz ADC? Does it meet the requirements I have pointed out?  Cheers, Dave

[Altera_Forum]

"""""""""""""""""""""" 

One option is to use a direct digital synthesizer (DDS). Analog devices has many devices."  """""""""""""""""""""""  If I can use a DDS,why can I use FPGA. I know we can use FPGA make a DDS.    """"""""""""""""""""""  "The sample rate of the ADC does not have to vary at all. You can vary the sample rate once you have the data on the FPGA using multi-rate sampling and digital filtering. While this may seem more complex, it may in fact be simpler, in that your ADC operates at a fixed frequency. For example, I run my 1GHz ADCs at 1GHz all the time. Digital filters are then used to generate 250MHz, 125MHz, etc, down to 2MHz sampling modes.  """"""""""""""""""""""  I think is a solution about this.I thougt it before.I can just change the write cloclk of FIFO with timing sampling( don't know how to use digital filter to realize it). However, how can I control it when using equivalent sampling.  Yes you are right, I have a sample-and-hold in front of ADC.So ADC is not a problem. My problem is I need control the clock to change the the sampling rate.If the signal in the low frenquecy,I just need change the frequency of clock. while in the high frenquecy,I need use equivalent sampling (it's need complex control so that create equivalent sampling pluse).Now I can create the right sampling pluse with FPGA, but the pluse output from FPGA is bad,so that ADC is not work properly!  I am grateful for your help! Thank you very much!

[Altera_Forum]

--- Quote Start ---    If I can use a DDS,why can I use FPGA. I know we can use FPGA make a DDS.    --- Quote End ---  It all comes down to how low you can get the clock jitter. The dividers in a DDS are designed with low-jitter in mind.    --- Quote Start ---    I have a sample-and-hold in front of ADC.So ADC is not a problem.   --- Quote End ---  How is the clock to the sample-and-hold generated? If it is from the FPGA, then you need to have very low sampling jitter.    --- Quote Start ---   My problem is I need control the clock to change the the sampling rate.If the signal in the low frenquecy,I just need change the frequency of clock. while in the high frenquecy,I need use equivalent sampling (it's need complex control so that create equivalent sampling pluse).   --- Quote End ---  The digital control is not complex; it is the triggering that is complex.  For the digital control, you would generate a 200MHz time-base, and then decide how often to sample. If you sample every 199 clocks, then the sampling frequency is ~1MHz and the sampling location relative to a 200 period 1MHz signal is 1 clock earlier, if you sample every 201 clocks, then the sampling location is 1 clock later. After 200 samples, you will have a full period at 200MHz and you can reconstruct your signal.   This will of only work if you have a trigger to start the sampling at exactly the same instant every time. Oh yeah. the trigger needs to have low jitter ...    --- Quote Start ---   Now I can create the right sampling pluse with FPGA, but the pluse output from FPGA is bad,so that ADC is not work properly!    --- Quote End ---    You have not explained what is 'bad' about your FPGA output clock. Could you perhaps describe what you have done, or show a circuit diagram, and maybe post an oscilloscope trace.   Cheers, Dave

[Altera_Forum]

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This will of only work if you have a trigger to start the sampling at exactly the same instant every time. Oh yeah. the trigger needs to have low jitter ...   I don't know why I need a trigger to start the sampling. I think I just need to count(assume the count value is N) in a period of the signal by 200M clock to get the period.Sample one point per N+1 cycle,and then I can get a 200M equivalent sampling rate(If I use 100M clock ,I can get a 100M equivalent).  The trigger is a problem.Because I need to measure the period of signal(as I mentioned before,counting in a period of the signal by 200M clock ). I can't adjust the signal to a square wave with a low jitter. It confused me for a long time.

[Altera_Forum]

Your intentions to build an equivalent sampling system have been wll understood. But the doubt was about the sample-and-hold bandwidth and aperture uncertainty of your ADC. The latter would also decide, if it's reasonable to generate the ADC sample clock inside the FPGA.  

 Related to the jitter performance of high speed ADC, the FPGA clock tree is not so good, but I guess, it can keep with your 1 MHz ADC respectively the involved S/H circuit.  P.S.: A more continuous phase interpolation beyond the capabilities of the digital DDS part can be achieved with the PLL dynamic phase shifting feature of newer FPGAs,  Another option is to derive the sample event from an analog interpolated DDS signal, as e.g. provided by the Analog Devices DDS chips.  But I didn't yet hear about the aperture jitter of your ADC which is the basic hardware limitation for the system.

[Altera_Forum]

--- Quote Start ---   I don't know why I need a trigger to start the sampling.   --- Quote End ---  Create a picture of a 3MHz sinusoid sampled at 200MHz. Now draw your 1MHz samples on that picture.  The naive thing to do, would be to draw the ~1MHz samples so that they accumulate next to each other on top of the 200MHz samples of the 3MHz sinusoid. This makes the unlikely assumption that your sinusoid is phase-locked to your FPGA clock and that you already know the input signal period.  Now draw 200 3MHz sinusoids with random phase.  Now how do you collect N-samples from these sinusoids and reconstruct the sinusoid? The answer is the trigger. For example, lets say your trigger can detect the zero crossing of the sinusoid, then that zero crossing event gives your repetitive sampling a reference point from which to capture samples; the 200MHz effective sampling rate is the reconstruction of N-samples spaced in time 1/200MHz apart relative to the trigger position.    --- Quote Start ---   I think I just need to count(assume the count value is N) in a period of the signal by 200M clock to get the period.Sample one point per N+1 cycle,and then I can get a 200M equivalent sampling rate(If I use 100M clock ,I can get a 100M equivalent).    --- Quote End ---  Unless the signal you are looking at is the same each time, you will just be sampling random parts of the incoming waveform.    --- Quote Start ---    The trigger is a problem.Because I need to measure the period of signal(as I mentioned before,counting in a period of the signal by 200M clock ). I can't adjust the signal to a square wave with a low jitter. It confused me for a long time.  --- Quote End ---  You are creating more problems by trying to solve this problem with an interlaced sampling scheme.  Cheers, Dave

[Altera_Forum]

I think you are talking about random sampling, so it need the trigger. But I use the sequence sampling(I think random sampling is harder than sequence sampling). I just need one trigger (or a reset ) to start the sampling, while needn't trigger at every sample point. 

First,I get the count value of one period of signal(count at main clock).Then, I sampling one point per N+1 cycles. I don't know that it is good method or not .   I am very confused at the signal processing of FPGA(include the input signal and output signal,as I said before the output signal wave is bad and FPAG need low jitter input signal). Do you have any idea to deal with the problem.

[Altera_Forum]

Related to the jitter performance of high speed ADC, the FPGA clock tree is not so good, but I guess, it can keep with your 1 MHz ADC respectively the involved S/H circuit. 

Does the output clock become good if I use the PLL of FPGA? =======================  Another option is to derive the sample event from an analog interpolated DDS signal, as e.g. provided by the Analog Devices DDS chips.   DDS chips output sinusoid.How can I use it to derive ADC?(add a compator?)  ========================= But I didn't yet hear about the aperture jitter of your ADC which is the basic hardware limitation for the system.  --- Quote End ---    I don't understand the jitter of ADC. I think the if the clock isn't beyond the maximum frenquency,the ADC can work properly.