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i want to read an image (or preferably a matrix of size 8x8) pixel by pixel in one clock cycle(if rising edge then read one pixel in 2nd rising edge 2nd pixel)....thanks in advance
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And what is your question?
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Sounds like a normal project. Whats the problem?
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i have got the code to extract row wise in each clock cycle.... How to extract pixel by pixel in each clock cycle.....and store it in another matrix....
i have to do Discrete wavelet transform on images by lifting scheme.- Mark as New
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my project is to perform discrete wavelet transform of image...for which i have to implement lifting scheme on image...which needs to extract even and odd pixels of the respective image.....
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--- Quote Start --- i have got the code to extract row wise in each clock cycle.... How to extract pixel by pixel in each clock cycle.....and store it in another matrix.... i have to do Discrete wavelet transform on images by lifting scheme. --- Quote End --- Use a counter as the index into the array? Why not try and code this yourself and we can help with problems? we are not going to do your work for you...
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--- Quote Start --- Use a counter as the index into the array? Why not try and code this yourself and we can help with problems? we are not going to do your work for you... --- Quote End --- i have done some modifications in the code....please help with the code
package newtype is
type row_t is array(0 to 3) of integer;
type matrix_t is array(0 to 3, 0 to 3) of integer;
type row_pixel is array (0 to 0) of integer;
end newtype;
--function to extract each pixels of a row
function extract_row_pixel(row1 : row_t; pixel : integer) return row_pixel is
variable ret_pixel : row_pixel;
begin
for i in 0 downto 3 loop
ret_pixel(i) := row1(pixel, i);------error is Type integer is not an array type and cannot be indexed.
end loop;
return ret_pixel; ------error is Expecting type row_pixel for <ret_pixel>.
end function;
if rising_edge(clk) then
temp_row_pixel <= extract_row_pixel (output, to_integer(count));
count <= count + 1;
output1 <= temp_row_pixel;
end if;
error is :
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For a start, this is never going to work. It looks like you're trying to write sofware. This is clearly not the full code as there are lots of things missing (like a process, architecture, etity etc).
So errors in your code: row_pixel is an array of length 1. Your for loop also never executes as you have 0 downto 3 (a null range). I suggest you go back to the drawing board - literally. DRAW your intended circuit on paper before you write any VHDL. VHDL is a hardware description language. Not a programming language. Writing code like software will not work.- Mark as New
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--- Quote Start --- For a start, this is never going to work. It looks like you're trying to write sofware. This is clearly not the full code as there are lots of things missing (like a process, architecture, etity etc). So errors in your code: row_pixel is an array of length 1. Your for loop also never executes as you have 0 downto 3 (a null range). I suggest you go back to the drawing board - literally. DRAW your intended circuit on paper before you write any VHDL. VHDL is a hardware description language. Not a programming language. Writing code like software will not work. --- Quote End ---
---main code
package newtype is
type row_t is array(0 to 3) of integer;
type matrix_t is array(0 to 3, 0 to 3) of integer;
type row_pixel is array (0 to 0) of integer;
end newtype;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.newtype.all;
entity test is
port(input: in matrix_t;
clk: in std_logic;
output : inout row_t;
output1 : out row_pixel);
end test;
architecture arch of test is
signal matrix : matrix_t;
signal temp_row : row_t;
signal temp_row_pixel : row_pixel;
signal count : unsigned(1 downto 0) := "00";
--signal output: row_t;
--function to extract rows
function extract_row( m : matrix_t; row : integer) return row_t is
variable ret : row_t;
begin
for i in row_t'range loop
ret(i) := m(row, i);
end loop;
return ret;
end function;
--function to extract each pixels of a row
function extract_row_pixel(row1 : row_t; pixel : integer) return row_pixel is
variable ret_pixel : row_pixel;
begin
for i in 0 to 3 loop
ret_pixel(i) := row1(pixel, i);
end loop;
return ret_pixel;
end function;
begin
process(clk)
begin
if rising_edge(clk) then
temp_row <= extract_row( input, to_integer(count) );
count <= count + 1;
output <= temp_row;
temp_row_pixel <= extract_row_pixel (output, to_integer(count));
count <= count + 1;
output1 <= temp_row_pixel;
end if;
end process;
end arch;
---testbench
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
use work.newtype.all;
entity test_tb is
end;
architecture bench of test_tb is
component test
port(input: in matrix_t;
clk: in std_logic;
output : inout row_t;
output1 : out row_pixel);
end component;
signal input: matrix_t;
signal clk: std_logic;
signal output: row_t;
signal output1 : row_pixel;
constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;
begin
uut: test port map ( input => input,
clk => clk ,
output => output,
output1 => output);
stimulus: process
begin
input <= ((0,1,2,9), (3,5,6,10), (9,8,11,2), (9,7,1,6));
wait for 50ns;
stop_the_clock <= true;
wait;
end process;
clocking: process
begin
while not stop_the_clock loop
clk <= '1', '0' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;
end;
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Why bother declaring row_pixel at all? its just an array of length 1, why not just return an integer?
Why are you using an inout for output? this is bad practice the error is here: for i in 0 to 3 loop ret_pixel(i) := row1(pixel, i); end loop; ret_pixel is a row_pixel type with a range 0 to 0. Your loop is going out of range.- Mark as New
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And why not just the count signal to access into the image?
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--- Quote Start --- Why bother declaring row_pixel at all? its just an array of length 1, why not just return an integer? Why are you using an inout for output? this is bad practice the error is here: for i in 0 to 3 loop ret_pixel(i) := row1(pixel, i); end loop; ret_pixel is a row_pixel type with a range 0 to 0. Your loop is going out of range. --- Quote End --- what should i write if i have to extract each value from the row (output) in each clock cycle....
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what about something simple like this?
signal row, col : unsigned(1 downto 0) := "00";
process(clk)
begin
if rising_edge(clk) begin
output <= input(to_integer(row), to_integer(col));
col <= col + 1;
if col = "11" then
row <= row + 1;
end if;
end if;
end if;
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I want to follow this algorithm :
d(n)=output(2n+1)-(1/2)[output(2n)+output(2n+2)] where output is an array consisting of 64 values... after each clock cycle d(n) gets a definite value based on calculation so according to this algorithm d(n) must contain 31 values... ---main code package newtype is type row_t is array(0 to 63) of integer; type approx_t is array(0 to 30) of integer; type matrix_t is array(0 to 7, 0 to 7) of integer; end newtype; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.newtype.all; entity test is port(input: in matrix_t; clk: in std_logic; output : inout row_t; d : out approx_t); end test; architecture arch of test is signal matrix : matrix_t; signal temp_row : integer; signal temp_approx : integer; signal i : unsigned(5 downto 0) := "000000"; signal n : unsigned(4 downto 0) := "00000"; signal count : unsigned(6 downto 0) := "0000000"; signal limit : unsigned (6 downto 0) := "1111111"; signal row, col : unsigned(2 downto 0) := "000"; begin process(clk) begin if rising_edge(clk) then temp_row <= input(to_integer(row), to_integer(col)); output(to_integer(i)) <=temp_row; col <= col + 1; if col = "111" then row <= row + 1; end if; i<=i+1; count <= count + 1; -----here i am trying to waste some clock cycles, because after few clock cycles only required number of outputs will be available for operation. if count >= limit then temp_approx <= output(2*((to_integer(n)))+1)-0.5*(output(2*((to_integer(n))))+output(2*((to_integer(n)))+2));--error: Found 0 definitions for operator "*" d(to_integer(n)) <= temp_approx; n<= n+1; end if; end if; end process; end arch; ---testbench library IEEE; use IEEE.Std_logic_1164.all; use ieee.std_logic_unsigned.all; use IEEE.Numeric_Std.all; use work.newtype.all; entity test_tb is end; architecture bench of test_tb is component test port(input: in matrix_t; clk: in std_logic; output : inout row_t; d : out approx_t); end component; signal input: matrix_t; signal clk: std_logic; signal output: row_t; signal d: approx_t; constant clock_period: time := 0.1ns; signal stop_the_clock: boolean; begin uut: test port map ( input => input, clk => clk , output => output); stimulus: process begin input <= ((0,1,2,9,10,5,8,4), (3,5,6,10,2,9,10,5), (9,8,11,2,10,2,9,10), (9,7,1,6,10,2,9,10),(1,4,5,3,6,10,8,9),(14,2,3,5,6,7,8,9),(9,7,1,6,10,2,9,10),(12,4,7,8,9,2,12,0)); wait for 50ns; stop_the_clock <= true; wait; end process; clocking: process begin while not stop_the_clock loop clk <= '1', '0' after clock_period /2; wait for clock_period; end loop; wait; end process; end; error is : Found 0 definitions for operator "*". please tell where is the mistake ?? Thanks in advance- Mark as New
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you cannot multiply unsigned type and real type (0.5). Real type is not suitable for synthesis. Try /2 instead.
But I still think you have real issues with your architecture. It is very inefficient and written as if it was software. Why do you have to "waste" clock cycles? Also - what external interfaces are you using? I doubt there are enough pins to output an entire 8x8 array - so why not do the calcualtions serially? Have you drawn out your circuit on paper?- Mark as New
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wasting clock cycles means the algorithm should start after some defined clock cycles
yes i have drawn circuit on paper... the thing is i am trying to do the project first on a small matrix of 8x8... if the algorithm works properly then i will implement with the complete 512x512 image- Mark as New
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With a 512x512 image - you need to use ram. There will not be enough resources to store an entire image in registers (and it would take forever to compile).
You need to rethink your design.- Mark as New
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--- Quote Start --- With a 512x512 image - you need to use ram. There will not be enough resources to store an entire image in registers (and it would take forever to compile). You need to rethink your design. --- Quote End --- I understand that sir completely... But currently i have to work with a small matrix only...once algorithm is developed it is not very difficult to apply it to a full size image.. (i have generated the hex file of the image from MATLAB, all i need is to load each value from that file with every clock cycle, hence i am trying to develop the code for algorithm first...)
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yes temp_aprrox, output gets reasonable values .
and yes row and col are correct at the correct times. only problem is with "d"....- Mark as New
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I think you have replied to the wrong forum - but do you realise that D will only take 1 value every 128 clocks, so it will take 8192 clocks to complete every value in the D array? Until they are set, D(r,c) will have the value -2^31.
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I have changed the code like this:-
for 0 to 64 clocks output will be extracted and once clock pulses exceed 64 (i.e., count value exceeds 64) algorithm will start and values will be loaded into d. ---main code package newtype is type row_t is array(0 to 63) of integer; type matrix_t is array(0 to 7, 0 to 7) of integer; type approx_t is array(0 to 30) of integer; end newtype; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.newtype.all; entity test is port(input: in matrix_t; clk: in std_logic; output : inout row_t ; d : out approx_t); end test; architecture arch of test is signal matrix : matrix_t; signal temp_row : integer; signal i : unsigned(5 downto 0) := "000000"; signal row, col : unsigned(2 downto 0) := "000"; signal count : integer := 0; signal limit : integer := 64; signal n : unsigned(6 downto 0) := "0000000"; signal temp_approx : integer; begin process(clk) begin if rising_edge(clk) then if count < limit then temp_row <= input(to_integer(row), to_integer(col)); output(to_integer(i)) <=temp_row; col <= col + 1; if col = "111" then row <= row + 1; end if; i<=i+1; else temp_approx <= output(2*((to_integer(n)))+2)-(1/2)*(output(2*((to_integer(n)))+1)+output(2*((to_integer(n)))+3)) ; d(to_integer(n)) <= temp_approx; n<= n+1 ; end if; count <= count + 1; end if; end process; end arch; but still d contains garbage- Subscribe to RSS Feed
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