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Honored Contributor I

interfacing to epcq256 through fpga



I've posted this before buy I'm trying to interface to the EPCQ256 of my dev board ( via the fpga in order to store a counter on it. I am using the asmi parallel core ( in order to do this; however, the busy signal coming from the epcq needs to be low before I can start executing commands on it. Right now the busy signal is almost always high so I cant execute anything because of this. I've attached a screenshot of the busy signal coming from the epcq.  

Also when the busy signal is low it is low for exactly 2 clock cycles which I'm wondering if it has anything to do with this from the datasheet: 


--- Quote Start ---  

When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command. 

--- Quote End ---  



This is not making sense to me and any help with this would be greatly appreciated.
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