Honored Contributor II
11-20-2017 07:06 PM
Hello,I've posted this before buy I'm trying to interface to the EPCQ256 of my dev board (http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=167&no=816) via the fpga in order to store a counter on it. I am using the asmi parallel core (http://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_altasmi_parallel.pdf) in order to do this; however, the busy signal coming from the epcq needs to be low before I can start executing commands on it. Right now the busy signal is almost always high so I cant execute anything because of this. I've attached a screenshot of the busy signal coming from the epcq. https://alteraforum.com/forum/attachment.php?attachmentid=14436&stc=1 Also when the busy signal is low it is low for exactly 2 clock cycles which I'm wondering if it has anything to do with this from the datasheet: --- Quote Start --- When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command. --- Quote End --- This is not making sense to me and any help with this would be greatly appreciated.