know factory settings for CycloneIII

[Altera_Forum]

Hi, 

I am new to FPGA designs. I want to Develop a board which will have a CycloneIII device. This device has to be configured by an parallel flash (P30).   I am really confused abt the first time booting up of the FPGA, as how will the configuration code for the FPGA (which has to be taken from flash) get into the Flash device?    and also can any body please explain me abt the pin-out excel sheet of the FPGA EP3C16, it says that some of the pins are dual purpose for configuration and IO (for flash interface data,addr,control), so if these pins are dedicated , does the fpga aleady have a flash memory controller, even before configuring it for the first time ?

[Altera_Forum]

Yes, the FPGA has a flash controller, that's the reason why you have to use dedicated pins for the flash. The selection of active parallel (flash) configuration is through hardware pinstrapping with MSEL pins. 

 For initial flash programming, a JTAG interface should be additionally provided.

[Altera_Forum]

thanks for your quick reply... 

so the FPGA has a flash controller as well as JTAG hardware support even if it is not even configured for a single time ? it has both of the above features when it is rolled out of the FAB .?

[Altera_Forum]

Yes. In the active configuration modes, either AS (active serial) for serial flash or AP (active parallel), the FPGA starts to read the configuration after power-on reset or an external configuration request. JTAG configuration and boundary scan function is always available, independant of the selected configuration scheme.