Hi all, I use an unconventional programming style. My FPGA designs work almost without problems. However, in the synthesis I get the warning message: "inferring latch(es) for signal or variable" r ", which holds its previous value in one or more paths through the process".
It makes sense for me, as it is registers within the record, which may not change their value. Does this possibly affect the created FPGA circuit?
The code below is just a basic example, regardless of syntax errors.
entity modul_abc is port( clk: in std_logic; rst_n: in std_logic; input_in: std_logic_vector(3 downto 0); output_out: std_logic_vector(3 downto 0) ); end entity; architecture arch of modul_abc is type T_REG is record abc : natural; efg: std_logic; xyz : std_logic_vector(3 downto 0); end record; constant C_REG_DEFAULT : T_REG := ( abc => 0, efg => '0', xyz => (others => '0') ); signal r : T_REG := C_REG_DEFAULT; begin output_out <= r.xzy; process(rst_n, clk) variable v : T_REG := C_REG_DEFAULT; begin if rst_n = '0' then r <= C_REG_DEFAULT; elsif rising_edge(clk) then v := r; v.abc := r.abc +1; v.xyz := input_in; r <= v; end if; end process; end architecture;
It is bad practice to infer any latches, especially because they can cause a mismatch between simulation and synthesis. My question is why do you even need the variable v? Just update r.abc and r.xyz directly each clock cycle. But to avoid the inferred latch, you could probably just add: r.efg <= r.efg;
I see, I made a mistake. I used a two process method since my first FPGA days as described here:
I thought these programming style could combine the advantage of this method, using r for actual state and v for further register state, in a process. But this seems not to work in the same way.