lpm_ff megafunction

[Altera_Forum]

I am analyzing an old design of an FPGA that looks like it is clocking data in with the lpmFF megafunction set up as a D flip flop. But looking at the input data with an analyzer, the input data goes valid after the rising edge of the clock input to the megawizard flip flop so it seems like a D flip flop would not work properly. Typically a D flipflop sets the output to the input on the rising edge of the input clock. Just wondering if there is a way to set up the lpm_FF megafunction to have the output follow the input when the clock signal is high and then latch the output when clock goes low as perhaps this is what is going on? Also is there a way to simulate what the design will do by entering simulated input signals?

[Altera_Forum]

--- Quote Start ---  I am analyzing an old design of an FPGA that looks like it is clocking data in with the lpmFF megafunction set up as a D flip flop. But looking at the input data with an analyzer, the input data goes valid after the rising edge of the clock input to the megawizard flip flop so it seems like a D flip flop would not work properly. Typically a D flipflop sets the output to the input on the rising edge of the input clock. Just wondering if there is a way to set up the lpm_FF megafunction to have the output follow the input when the clock signal is high and then latch the output when clock goes low as perhaps this is what is going on? Also is there a way to simulate what the design will do by entering simulated input signals?  --- Quote End ---    Hi,  what exactly is your problem ? The FF behaves in the right way. After a short time behind the rising edge of the clock ( clock-to-output delay) the output will change to input value.  Kind regards  GPK

[Altera_Forum]

Thanks for the response, just looking at the data that is feeding into the megafunction it looks like a D flip flop operation would not clock the data in properly, again this is an existing design. The data feeding into the megafunction has the clock go high with data arriving after the rising edge of the clock.

[Altera_Forum]

Thats normal. The delay is from the set-up time of the data. Ie, it changed at this rising edge of the clock on the previous register, and at this register it will be clocked on the next clock edge. Are you having problems with setup and hold times?

[Altera_Forum]

thanks for the additional information, I will look at the setup and hold times. I was thinking that for example if the input data to the D flip flop is a 1, it would have to be set high by the time the rising edge of the clock arrived to the D flip flop in order for the output Q to be driven high. I have 

  ******** ********  clk in ** ******** ******    ** data in ***** *******************   So to me it looked like the data whould not be clocked in by the FF.

[Altera_Forum]

you text diagram makes no sense. Try using the code tags to light text up.

[Altera_Forum]

Looks like the previous timing diagram got messed up, I have included a txt file showing input signals to the megawizard, thanks.

[Altera_Forum]

--- Quote Start ---  Looks like the previous timing diagram got messed up, I have included a txt file showing input signals to the megawizard, thanks.  --- Quote End ---    Hi,  you have to keep the required timing conditions in order to get the right functionality. The input data needs to stable a certain time before the active edge ( setup requirement) and needs to stable for a ceratin time after the active edge ( hold time requirement).  The output of your FF will be always "0" with the given timing diagramm. Have a look to the attached file.   Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Looks like the previous timing diagram got messed up, I have included a txt file showing input signals to the megawizard, thanks.  --- Quote End ---    The diagram you give shows the '1' value of data is more a glitch than a real data value, and is rightly ignored.  pletz has given you a diagram of what should really happen.

[Altera_Forum]

thanks for the replies, I think something is going on with the input data. I also ran a simulation to verify the behavior.

[Altera_Forum]

I noticed that the lpm_ff megafunction has been removed from Quartus 10.1. 

 Is there any other similar megafunction that can be used to delay the input, for example, by 5 clock periods? I don't want to use 5 dff blocks.  Thank you.

[Altera_Forum]

try a shift register?

[Altera_Forum]

I was looking into the lpm_shiftreg megafunction and am a little confused. 

 I basically want to delay a 16-bit input to a multiplier by 5 clock periods. I did not find any option in the MegaWizard for lpm_shiftreg to set the desired time delay. Any help will be appreciated.

[Altera_Forum]

a shift register is really just a chain of flip flops.

[Altera_Forum]

Yeah I cascaded a few flip-flops together and my design is working. I also read in the User Guide for lpm_shiftreg that this megafunction is not supported by the device I am implementing on; hence I will go with the cascade. 

 Thanks.