m25p26

[Altera_Forum]

Hi everybody, 

 I have finished a pcb design with a cyclone III Ep3c25q240, it is configurated in AS mode. There are two connector (10 pins), one for the JTAG and the other for the AS. When I download the .sof file into the FPGA (in JTAG mode with the JTAG connector and the usb blaster cable) there is no problem, but when I try to run the nios2 app it says it cannot reset the nios uP. Also, when I try to configure the flash (m25p16) with the .pof file there is no movement in te configuration progress bar in the quartus2 programmer (in AS mode with the AS connector and the usb blaster cable).  Any help?

[Altera_Forum]

It could be a good idea to check the signals on the flash with an oscilloscope to see if there is any hardware problem. You can also configure the FPGA with an SFL image and try to access the flash through the JTAG connector. 

As for your Nios design, there could be a number of reasons, such as timing problems on your FPGA project, bad clock input, or processor kept into reset (be careful with the reset signal, the reset_n port created by SOPC builder is active low, not high). You could try to do a simpler design first, with no CPU and just a flashing led as an example, to check that the FPGA and its clock source are working properly.

[Altera_Forum]

I have seen that instead of a clean external clk of 50 MHz, I have a clk of 1KHz. I'm confused because the circuit apparently seems correct. I attach the schematic, If anyone can help I would be grateful. Thanks. 

 Also the AS interface doesn`t work.

[Altera_Forum]

i also would start with a simpler design. the Sources and Probes function can be useful during board bring up 

  you could try to configure the AS device using JTAG with a .jic file

[Altera_Forum]

The problem in the clock seems fixed, there was a short circuit between the case of the oscillator and one of his path. Now I have tried to configure the flash and the fpga with the jic file, but without success. I think something is wrong in the AS interface. I also have run succesfully the source&probe test with a switch and one led.

[Altera_Forum]

I have measured with the scope some pins, for example in nCE appears a voltage of 0.8v and in nSTATUS 1.8V, nCONFIG 2.5v and CONF_DONE 2.5V. The banks of the fpga are fed by 2.5v. Also I have probed the SFL design and the flash doesn`t configure with the jam file (no device id identification). I attach two captures with the logic analyzer in the AS interface. The first one when I plug in the board and it tries to configure itself, and the second one when I try to configure the flash via the SFL driver.

[Altera_Forum]

Do you ever have anything on the DATA0 signal? It's strange that the flash never replies anything. It could be interesting to probe both terminals of the 25 Ohm resistor with an oscilloscope.

[Altera_Forum]

There was a short circuit in the schottky array diodes, now the flash can be programmed through the JTAG and the AS interface. The next challenge is making nios run properly in the board, because when I configure it through eclipse it says Downloading to memory but verification failed between the address corresponding to the DDR memory. I will check the paths to the memory. At least the "hello world" example with on-chip memory works.

[Altera_Forum]

Now the program is downloaded into the ddr and the verification is ok but 

it appears an error with the jtag debug (m_state = STATE_DEBUG failed).  Is there any method to check the ddr good-working? I'm using a SAMSUNG k4h561638n-lccc instead of a k4h561638f-tccc, which timing presets come in the ddr-controller altera megafunction. Maybe with a logic analyzer... but it would be a hard work taking from the board all the signals.   Many thanks,  ifdm

[Altera_Forum]

You can try and create a design with a big on-chip memory for the CPU and run a memory test program from there. In Eclipse when you create a project, you have a memory test template that you can use, just ensure that the BSP is defined to only use the onchip memory for everything (text, bss, stack, heap...). You'll also probably have to turn on optimisations and use the small C library to make everything fit in the on-chip memory.

[Altera_Forum]

I have just run the mem test but after filling the start and the end address ( all the ddr memory region and only parts of it) the program stops and nothing appears.  

 Many thanks for the advice.

[Altera_Forum]

There could be a number of reasons that make the application crash or the CPU freeze. 

First ensure that no part of your application resides in the DDR. This includes heap and stack. If any of those are in the DDR the CPU will erase them while running the memory test. Check also that the address you enter is the right one (but I guess you already checked that). You can put some signaltap probes on the DDR controller's Avalon interface to see if it's doing anything during the test.

[Altera_Forum]

I have debug the mem_test app and it stops when it's made an IORD in the ddr. I also have test the app with the signaltap but it doesn`t seem that it's working properly.  

  I think it could be a problem with the memory presets or maybe with the sttl2-standard. I use a serial resistance of 10 ohm (in dq pins) and 22 ohm (the rest ddr pins) for the driver; and 56 ohm attached to 1.25V in the load. ( I have omitted this bus termination for ras,cas,we,dm, ck, and dqs signals)  Thankyou in advance.

[Altera_Forum]

I have no experience with DDR memories unfortunately so I can't help you there. 

With SignalTAP you can at least check if the DDR controller is stalling the CPU with the waitrequest signal. Did you check the I/O timing constraints, and that timequest doesn't complain about timing? Altera also has a memory interface debugging document (http://www.altera.com/literature/hb/external-memory/emi_debug_hw.pdf), you may find ideas there.

[Altera_Forum]

When I try to debug the ddr commands with signaltap, some illegal and missing sources appear: 

 basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_cas_n basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_ras_n basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_we_n  " DDIO I/O pins cannot be tapped directly. Tap the hi/lo channels separately."  and   basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_cke basic_sopc:inst2|altmemddr_0:the_altmemddr_0|mem_cs_n  "The pre-synthesis tap must be preserved by Analysis & Synthesis before it can be tapped. Set the partition's netlist type to Source and recompile."