mSGDMA ST -> MM DDR3 Uniphy optimal seetings for bandwidth

[Altera_Forum]

I'm streaming video data through the mSGDMA to DDR3 memory with the uniPHY memory controller in Qsys. I'm using a version of the example c code from the mSGDMA wiki to measure throughput. As it is, the best I can achieve is ~175 MB/s.  

 I'm hoping someone could give me some advice regarding the settings of the mSGDMA write master and the uniphy controller. My current settings are below. I've played around with the burst settings but it seems to have no effect. I've also put the data path up to a higher clk (50MHz -> 125 MHz) but that decreased the throughput to 45 MB/s. I'm learning more about how bursting works with DDR3 etc but so far I havent been able to improve on 175 MB/s. Any advice would be great!  write_master:   

• Data_Width: 256 
• Length_Width: 26 
• FIFO_Depth: 4096 
• Burst_Enable: Ticked 
• Burst_Count: 32 
• Force Burst Aligment: Ticked 
• Transfer Type: Aligned Acesses 
• Packet Support Enable: Ticked 

  ddr3 controller:   

• Enable Hard controller: Ticked 
• Speed Grade: 7 
• Mem clock freq: 400MHz 
• PLL ref clk: 125MHz 
• Rate on Avalon MM: Full 

   

• Device Speed Grade: 800MHz 
• Interface width: 32 
• DQ/DQS Group size: 8 
• Rows: 12 
• Cols: 10 
• Bank addr width: 3 

   

• Read burst type: Sequential 
• Auto self refresh: Manual 

   

• Max burst length: 32 

  I'm running on the Cyclone V dev board for now with a 32 bit interface to the DDR3.   I understand the FIFOs etc may not be the most efficient set up, but for now I'm trying to get the best possible throughput.