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Valued Contributor III
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maintaining my result from becoming unknown state

Hello,  

 

i've got a question on how to maintain my result from becoming unknown state. let's say the original value is 11110000. however after some period of time it becomes 1111X00X making the output become unknown. besides there are fuzzies during transition fron 11110000 to 1111X00X. what can i do to remove the fuzzies and eventually being able to maintain the result?  

 

i've tried adding delays such as  

 

result <= b and "0000000011111111" after 30 ns; 

 

but i did n't see any difference. is there any way to remove the fuzzies and getting a stable final output?
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Valued Contributor III
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If your design is synchronous you simply don't care about those unknown states, because those values of your output will be evaluated only at some clock edges. 

So you should care only about the values of your result in correspondence of your active edges of the clock, and ignore what's happening in between them. 

If your design is asynchronous, you'd better shift to a synchronous design, so add a clock that acts to synchronize all the state changes in your machine and give reliable results at every clock edge.
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Valued Contributor III
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FYI 

 

 

--- Quote Start ---  

 

result <= b and "0000000011111111" after 30 ns; 

 

--- Quote End ---  

 

 

Constructs like the above cannot be synthesized. 

 

It is likely that Quartus will ignore the after "30 ns" part.
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Valued Contributor III
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oooh, so this means that adding "after 30 ns" will be ignored. actually, what is the use of "after 30ns"? some vhdl books have included this line into their commands. i thought it can some how delay the result?  

 

i've design a component which works on asynchronous inputs however, those inputs to the component are clock driven. how can i ensure that my final result becomes an asynchronous result?
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Valued Contributor III
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hi mikedsouze, 

 

the "after 30ns" is for pre-synthesis simulation or generating test benches as input stimulus for pre or post-synthesized VHDL. 

 

from the comp.lang.vhdl faq (http://www.eda.org/comp.lang.vhdl/faq1.html):  

 

--- Quote Start ---  

After clauses in signal assignment statements are not synthesised as there is no hardware primitive that has a fixed but settable delay. (Usually the delay varies significantly with temperature, supply voltage, output loading and the like). In the best case they are ignored by the synthesis tool. Hence, the statement  

 

sig <= not sig after 10 ns;  

 

will not result in an inverter with a 10 ns delay. Most likely, an inverter will be synthesized, but no attempt is made to adhere to the delay specification. 

--- Quote End ---  

to get a stable output you will want to read about clocked processes and inferring flipflops.
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Valued Contributor III
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--- Quote Start ---  

oooh, so this means that adding "after 30 ns" will be ignored. actually, what is the use of "after 30ns"? some vhdl books have included this line into their commands. i thought it can some how delay the result?  

 

i've design a component which works on asynchronous inputs however, those inputs to the component are clock driven. how can i ensure that my final result becomes an asynchronous result? 

--- Quote End ---  

 

 

It is valid VHDL but for behavioural code only i.e. testbenches etc. It is not valid for RTL coding and hence synthesize. 

 

It is virtually impossible to synthesize something like a delay line into an FPGA architecture
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