I am using CPLD EPM7512AEQC208 and trying to port my proven design (working perfectly well on cyclone FPGA). When I compile the project, the reset signal which is pin no 182 in this case, is not recognized as a global reset signal by Quartus software. This signal gets reflected in "Non-global-High-Fanout-signals" list where it has Fanout value of 101. (screenshot attached)
I tried to declare this signal as "global control signal" in Assignment editor but didn't get any success. I even tried to Enable Device-wide-reset (DEV_CLRn) in General Tab of "Device and pin option", Here I don't get any option to set it (screenshot attached). This option is available for MAX II series CPLDs.
Somebody please guide me how to enable Global reset control signal for MAX 7000AE family of CPLDs. I have used Quartus version 8.0 as well as 13.0.
Thanks in advance.....
The device you are using, EPM7512AEQC208-7 has discontinued and no longer supported:
Also the Quartus version is way too old that later version might have updates that not available in older version.
I will transition the thread to community support. Community users will continue to help you on this thread. Thank you