Solved: max10 jtag and config pin - Intel Community

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

max10 jtag and config pin

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Could you review if my jtag pin and config pin ?

using pull up or pull down, pick solution is right?
clock using VCCIO, is right?

1 Solution

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Hello,

Yes, your connection for JTAG pins are correct.

regards,

Farabi

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541 Views

Hello,

Yes, your connection for JTAG pins are correct.

regards,

Farabi

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You may refer to guide from Pin Connection Guideline : https://cdrdv2-public.intel.com/669875/pcg-01018-683232-669875.pdf

regards,

Farabi

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Thanks a lot!

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