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Beginner
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multicycle path latency

Can I use a multicycle path to simply add latency without reducing effective clock speed?  I want to run at  300 MHz between registers A and B.  But I've got a negative setup slack. 

It's streaming data, so I don't care about the latency between A and B, I only care that B gets new data on every clock.  Is that possible with a multicycle path or is that just for logic that runs every N clock cycles?

 
 
Advance thanks,
Karol.
 
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Moderator
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Yes, you may use this method.


You can take a look this link on how to do it https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/tafs/tafs/tcl_p...


After doing the above, you should be able to see the result in timing analyzer. Check the behavior if this is the one you want.


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