multiple driver due to always enable I/O buffer

[Altera_Forum]

Hello everyone,  

I'm currently emulating a cpu with the below VHDL coding as one of my components. its purpose is to check the required bit whether set or clear and doing setting and clearing of the bit as well.      library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use work.cpu_lib.all; entity flag is port(a :in bit16; b, en, clk :in std_logic; sel:in std_logic_vector(2 downto 0); c :out std_logic; d :out bit16); end flag; architecture rtl of flag is signal f: bit16; begin  f1:process begin wait until rising_edge(en); f <= a; case sel is  when "000" => if f(0) = '0' then c <= '0' after 1 ns; else c <= '1' after 1 ns; end if; if b = '1' then f(0) <= '1'; else f(0) <= '0'; end if;   when "001" => if f(1) = '1' then c <= '1' after 1 ns; else c <= '0' after 1 ns; end if; if b = '1' then f(1) <= '1'; else f(1) <= '0'; end if;  when "010" => if f(2) = '1' then c <= '1' after 1 ns; else c <= '0' after 1 ns; end if; if b = '1' then f(2) <= '1'; else f(2) <= '0'; end if;  when "011" => if f(3) = '1' then c <= '1' after 1 ns; else c <= '0' after 1 ns; end if; if b = '1' then f(3) <= '1'; else f(3) <= '0'; end if;  when "100" => if f(4) = '1' then c <= '1' after 1 ns; else c <= '0' after 1 ns; end if; if b = '1' then f(4) <= '1'; else f(4) <= '0'; end if;  when "101" => if f(5) = '1' then c <= '1' after 1 ns; else c <= '0' after 1 ns; end if; if b = '1' then f(5) <= '1'; else f(5) <= '0'; end if;  when "110" => if f(6) = '1' then c <= '1' after 1 ns; else c <= '0' after 1 ns; end if; if b = '1' then f(6) <= '1'; else f(6) <= '0'; end if;  when "111" => if f(7) = '1' then c <= '1' after 1 ns; else c <= '0' after 1 ns; end if; if b = '1' then f(7) <= '1'; else f(7) <= '0'; end if;  end case; end process;   f2:process(clk, f) begin if clk = '1' then d <= "00000000" & f(7 downto 0); elsif clk = '0' then d <= "ZZZZZZZZZZZZZZZZ"; else d <= "XXXXXXXXXXXXXXXX"; end if; end process; end rtl;   I tested it individually but i found no problem. when i tried to integrate the whole CPU, during the compilation these were the errors:   --Error: The pin "data[0]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[0]" --Error: The pin "data[1]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[1]" --Error: The pin "data[2]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[2]" --Error: The pin "data[3]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[3]" --Error: The pin "data[4]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[4]" --Error: The pin "data[5]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[5]" --Error: The pin "data[6]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[6]" --Error: The pin "data[7]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[7]" --Error: The pin "data[8]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[8]" --Error: The pin "data[9]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[9]" --Error: The pin "data[10]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[10]" --Error: The pin "data[11]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[11]" --Error: The pin "data[12]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[12]" --Error: The pin "data[13]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[13]" --Error: The pin "data[14]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[14]" --Error: The pin "data[15]" has multiple drivers due to the always-enabled I/O buffer "flag:flag0|d[15]"   i've tried to debug it but i could not able to remove the problem. can anyone advise me on this issue? thanks in advance.   mike

[Altera_Forum]

The errors isn't in thze code you're showing.