Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,013 Views

need set_max_delay understanding

Hi all, 

 

Can please some one explain that what is set_max_delay and what will happen it if is used on two clocks to meet setup slack inside FPGA? 

 

Kind regards 

Mohsin
0 Kudos
4 Replies
Altera_Forum
Honored Contributor I
149 Views

set_max_delay and set_min_delay are SDC constraints that override existing constraints. They are used if you want to specify to the Fitter a specific range of delay for a net. They should be used sparingly because you are just loosening timing if you choose values for them larger than what is selected based off of the clock constraints you specify. 

 

If you are failing setup timing on internal paths, you should probably not use set_max_delay. There is probably some other explanation for why you are failing timing, such as a long path delay due to physical constraints at the source or destination or you have too much combinational logic on the path. A really good solution is to add pipeline register(s) to break up long paths or logic.
Altera_Forum
Honored Contributor I
149 Views

Hi sstrell, 

 

Thank you for your reply. 

 

Can you please help me with following queries. 

 

1- Clock input to FPGA is 16MHz and is going to a PLL, which generates the 160 MHz clock, now this PLL clock is used as reference clock for input signals to FPGA. The question is that how will I write the constraint for input signals i.e. w.r.t 16 MHz or 160MHz? I have tried to do it like this, created a virtual clock of 160MHz and set_input_delay w.r.t to virtual clock but it gives timing failure with reference to PLL generated clock 

 

2- One of the input signals is an I/O signal and also asynchronous (coming from a micro-controller) how I can write the I/O constraints for this?  

 

 

Kind regards 

Mohsin
Altera_Forum
Honored Contributor I
149 Views

1) Remember that the virtual clock is the clock that drives the upstream (input) device. It defines the launch edge while your 160 MHz clock is the latch edge. What clock speed is driving that device?  

 

2) If it's truly asynchronous, just false path it. If it's not meant to be truly asynchronous, synchronize it with a register chain (at least two registers) and false path the input from the device port.
Altera_Forum
Honored Contributor I
149 Views

Hi sstrell, 

 

Thank you.  

 

1- The input devices are FPGA boards and clocking out the data at 40MHz. There is a customized serial interface between input FPGAs and main FPGA without any clock reference. The design is already working without any constraints and we want to constraint it to increase the processing speed of algorithm in the main FPGA. 

 

2- Yes, it is truly asynchronous, I will false path it but still I have to write the constraints with reference to a clock. 

 

kind regards 

Mohsin
Reply