Hello,Usually I work with std_logic_aritch and I include the package signed or unsigned according with what I need. I find that using std_logic_arith allows me to develop code that is easier to read, you do not have a lot of cast functions. I ask you , what is the advantage or disadvantage of using numeric_std instead std_logic_arith?. thank you. DABG
First the formal part:std_logic_arith is non-standard. The very fact that std_logic_arith is placed in ieee library is probably in violation with copyright and the vendors that did it were not taken to the court only because copyright holder was lazy or had no resources to do it. So by spreading std_logic_arith you likely support the violation of the low. Now to engineering part: Mixing signed and unsigned arithmetic in the same module with std_logic_arith is either very hard or may be impossible. Also the code is less readable because the reader should go to the header in order to figure out whether the arithmetic is signed or unsigned. If you fill that numeric_std is harder to use that's a sign that you are not accustomed to the proper coding style. As a rule, all signals/variables that are used in arithmetic statestments should be declared as signed, unsigned (for me, most of the time) or as integer ranges. std_logic_vector is used only for non-numeric signals and for interfacing with vendor libraries and with the outside world. Start using numeric_std exclusively and after one month you wouldn't understand how you thought that std_logic_arith is somehow good.
The problem is, that ieee.numeric_std has been introduced late. So the "non-standard" "ieee".std_logic_arith is still used at many companies that ones started with this synopsys originated lib. Altera does exclusively in all VHDL code, as far as I'm aware of.I agree about the limited use of the unsigned/signed libraries. The basic std_logic_arith library hasn't serious disadavantages in my opniuon, besides being non-standard.
numeric_std every time. It may have been introduced late, but that was 17 years ago! the problem is people reference old examples that are '87 standard and use std_logic_arith and stick to that.If you have loads of casts then I think you're using it wrong. Avoid using std_logic_vector when what you really mean is unsigned/signed or even integer. Ports on entities can be signed/unsigned or integer (with a limited range) so keep signals in the same type that you meant them to be, it makes it more readable. Avoid using altera megafunctions when you can imply them in the code (like using arrays to infer altsyncrams - you can use arrays of integers for this too!). You cannot do signed and unsigned arithmatic in the same file with std_logic_arith. If you ever tried to do fixed point arithmatic, you'd probably want to use numeric_std instead, or even better the new fixed point packages which are based on numeric_std. If you never have anything more than a counter or 2, then I can understand people sticking with std_logic_arith - but its best to build up a habit and stick with it. Many engineers I know that use are often building controllers and never do algorithm generation.