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Valued Contributor III
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phase delay of PLL

hello, 

i am implementing a PLL in EP3C16. 

there is round 2.5ns delay between the input reference clock and output clock. it seems that cyclone series FPGA including I,II,III all have a phase delay for PLL implmentation, but i am not sure about this, can anyone give men a definite answer? 

 

and i find in stratix fpga tht an extra 'fbin' input pin exists for PLL implementation, and i hear that a zeor phase delay PLL can be acheived using this 'fbin' pin, is that right? 

 

thanks.
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Valued Contributor III
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In general FPGA PLLs offer phase shift feature meausured in degrees or time with various degrees of step resolution. 

zero phase is just one value of phase that = 0 

zero phase buffer is the term used for having same clk output at same freq and phase as input and does not need external loop (fbin is only needed if you don't like the internal fpga analogue loop). 

 

If you mean to offset 2.5 ns between input clk and output then apply negative delay of -2.5ns
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Valued Contributor III
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--- Quote Start ---  

In general FPGA PLLs offer phase shift feature meausured in degrees or time with various degrees of step resolution. 

zero phase is just one value of phase that = 0 

zero phase buffer is the term used for having same clk output at same freq and phase as input and does not need external loop (fbin is only needed if you don't like the internal fpga analogue loop). 

 

If you mean to offset 2.5 ns between input clk and output then apply negative delay of -2.5ns 

--- Quote End ---  

 

 

thanks a lot. 

i designate -2.5ns phase shift when configuring PLL. 

the offset has now become to be less than 500ps. due to the step resolution, it can not be improved further. 

 

in fact, there is originally a 2.5ns delay when i left phase shift to 0, which puzzles me much. now i need to designate a negative value (as you say) to compensate it.
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Valued Contributor III
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If you connect your output to a dedicated PLL output pin ( the ones with an (L) in the pin-planner) you can set your PLL to compensate for this pin aligning the output clock with the input clock. See "Zero Delay Buffer Mode" on page 78 in the Cyclone III Device Handbook.

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