I am looking for the package pin delay data on the 1SX280LN2F43I2LG Stratix 10 FPGA for the High Speed I/O. I need that data to complete proper trace routing on the PWB. I also require any and all hardware design guidelines for the 1SX280LN2F43I2LG
Please refer to these following links:
1. Stratix 10 Device Datasheet: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_datasheet...
2. Stratix 10 GPIO User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-gpio.p...
3. Stratix 10 Device Family Pin Connection Guidelines: https://www.intel.com/content/www/us/en/programmable/documentation/lod1484643014646.html#mgd14846431...
I review went to the links that were listed in the response. I reviewed the data sheet, gpio guidlines, and pin connections guidelines and found no documentation on the high speed I/O package delay / p-n skew information. I also have been in contact with te FPGA devlopment team at Nokia and asked them to provide "Report Datasheet" option in TimingQuest Analyzer. In reviewing that report there was no mention of P-N skew on the high speead interfaces (10G and 25G lanes) Please provide some documentation on the p-n skew for each high speed lane.
Do you mean you are looking for IO Timing or IOE delay? You can refer to page 112 to generate IO Timing: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_datasheet...
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Sorry I was away on holiday. The data I am looking for is not IO timing, but it is the delay from the ball of the bga to the pad on the die. I have worked with other vendors that provide this delay for the differential pairs for 10G and 25G interfaces. I then take this delay for the P-rail and N-rail of a differential pair and import into the CAD database which then accounts for the p-n skew and allows me to reduce . minimize the over p-n skew.
Thank you for your support