problem about clock control block

[Justin569]

Hi,

When I use cyclone 10(10CL040YU484I7G)'s clock control block, I meet some problems.

In my application, there are 2 main clocks(one from clk pin and one from PLL), and 2 parts of main logic. I used 2 clock control blocks, and one for part A, the other for part B. But due to the inputs of 2 clock control blocks are same, Quartus says "Following nodes require the same Clock Control Block CLKCTRL_G10" in "place & route" phase.

Which logic will be chose which clock is only based on the clock chose logic. The clock chose logics of the two parts are independent. So I think I can't just use one clock control block.

I try to use LUT mux clock, but the quality of clocks are too bad to suit my application.What should I do? Why Quartus don't instence two Clock Control Block?

Thanks.

[sstrell]

Are you saying that you've manually added the clock control block IP (twice) to the design?  Try just coding the clock enable logic without the IP and see what happens.  Quartus will (should) add clock control blocks automatically or whatever logic is required.

[Justin569]

Hi sstrell, thanks for your attention. I directly used combinational logic for dynamical clock chosen before clock control block. But function didn't realised. Perhaps due to I hadn't constraint timming suitable. Nominally, the frequency of both master clocks is 125MHz. But the diffrence of frequency must exist. And they have diffrent phase. So I don't know how can I constraint the clock which chosen by combinational logic. Plase give me some guidance. Thank you.

[AqidAyman_Intel]

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