Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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problem getting started

Altera_Forum
Honored Contributor II
‎01-25-2011 09:26 PM
1,126 Views

Just getting started but tried to create a project and have a block diagram *.bdf file and a megafunction.qip and megafunction.vhd file for project files but when I try processing/start compilation I get the error, design entity "nameOfProject" is undefined. thanks.

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Altera_Forum
Honored Contributor II
‎01-25-2011 10:28 PM
193 Views

got it working, ended up setting the bdf file as top level entity.

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