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problem of lpm_mux in megafunction

Altera_Forum
Honored Contributor II
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I wish to know the sel function in megafunction of lpm_mux , is it edge trigger or level trigger ??

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Altera_Forum
Honored Contributor II
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edge triggered if its registered, level triggered if its not.

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Altera_Forum
Honored Contributor II
709 Views

do you mean that if quartus is registered then sel function is edge triggered ??

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Altera_Forum
Honored Contributor II
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no, if you chose to put a pipeline delay in the mux, then the clock edge triggers the device. If you have no pipeline delay, then there is no clock so it is level triggered on select.

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Altera_Forum
Honored Contributor II
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unless you're refering to voltages - do not concern yourself with voltage levels inside an FPGA device. Its all digital logic.

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Altera_Forum
Honored Contributor II
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Thanks tricky your answer is greatly helpful !!

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Altera_Forum
Honored Contributor II
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One more question if I choose put a pipeline delay in the mux , a clock input is created , can I short sel and clock together ? As I connect AD9481 to Cyclone III , It has a clock output , when rising edge indicate channel A is generated and when falling edge indicate channel B is generated .

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Altera_Forum
Honored Contributor II
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no, thats not recommended.

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Altera_Forum
Honored Contributor II
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The select line is sampled on the rising edge of the clock. So if sel = 0 then output = A, sel = 1 output = B. 

 

if you tied clock and select together, on the rising edge of clock, select would also be changing, and so you would have no garantee of A or B - you might even make it go meta-stable. 

 

And another point - you can only use a single clock edge inside an FPGA
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Altera_Forum
Honored Contributor II
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There is little info on lpm_mux in lpm.pdf.... 

 

Is it possible to use lpm_mux in pipeline mode to demultiplex a stream of 16-bit data @ 100MHz into two stream of 8-bit data @ 50MHz ? 

Can lpm_mux on the first rising edge of the clock select the first 8-bits out of 16-bits and on the second rising edge of the clock select the second 8-bits out of 16-bits and so on? 

I suppose that in this case Sel is ignored by lpm_mux?
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Altera_Forum
Honored Contributor II
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No. lpm_mux uses a single clock mux. You'll have to do the demuxing yourself.

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Altera_Forum
Honored Contributor II
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Sorry, I posted the wrong question (( 

Here is what I meant to ask: 

 

Is it possible to use lpm_mux in pipeline mode to multiplex two stream of 8-bit data @ 50MHz each into a single stream of 8-bit data @ 100MHz ? 

Can lpm_mux on the first rising edge of the clock select the first 8-bit stream and on the second rising edge of the clock select the second 8-bit stream and so on? 

I suppose that in this case Sel is ignored by lpm_mux?
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Altera_Forum
Honored Contributor II
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No. Its just a mux, Sel is always used and never ignored. You could easily do it though by having a toggle bit toggling at 2x data rate selecting the alternating halves of the wrod.

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