hi
i have a problem. Im working whit hdl design manager on de 2 board and i have opened Uart example project. This is my problem, when i run uart_tb to the simulator and i check Sout start bit it is 4 clk perioids long and the first actula bit is 9 clk perioids long and all next bits are 6 clk perioids long witch are right. So why are start bit and first bit different than the other bits and how can i change them.
SIGNAL int_clk : std_logic := '0';
SIGNAL read_data : std_logic_vector(7 DOWNTO 0);
CONSTANT CLK_PRD : time := 100 ns;
CONSTANT DIV_LSB : std_logic_vector(7 DOWNTO 0):= "00000110";
CONSTANT DIV_MSB : std_logic_vector(7 DOWNTO 0):= "00000000";
CONSTANT SER_DATA : std_logic_vector(7 DOWNTO 0) := "11001110";
CONSTANT XMIT_DATA : std_logic_vector(7 DOWNTO 0) := "01011011";
CONSTANT RCV_CLK_PRD : time := CLK_PRD * 6;
